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| to all our customers regarding the change of names ment ioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomput er, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitac hi, ltd., hitachi semiconductors, and other hitachi brand names are m entioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. ex cept for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: www.renesas.com renesas technology corp. customer support dept. april 1, 2003 renesas technology corp.
hitachi single-chip microcomputer h8/330 hd6473308, hd6433308, HD6413308 hardware manual preface the h8/330 is a high-performance single-chip microcomputer ideally suited for embedded control of industrial equipment. its core is the h8/300 cpu: a high-speed processor. on-chip supporting modules provide memory, i/o, and timer functions, including: 16k bytes of on-chip rom 512 bytes of on-chip ram 15 bytes of dual-port ram for a master-slave interface serial i/o general-purpose i/o ports a/d converter timers compact, high-performance control systems can be built using the h8/330. the h8/330 is available with either electrically programmable or mask programmable rom. manufacturers can use the electrically programmable ztat * (zero turn-around time) version to get production off to a fast start and make software changes quickly, then switch over to the masked version for full-scale production runs. this manual describes the h8/330 hardware. refer to the h8/300 series programming manual for a detailed description of the instruction set. * ztat is a registered trademark of hitachi, ltd. contents section 1. overview ............................................................................................................... 1 1.1 block diagram...................................................................................................................... 2 1.2 descriptions of blocks.......................................................................................................... 3 1.3 pin assignments and functions............................................................................................ 6 1.3.1 pin arrangement...................................................................................................... 6 1.3.2 pin functions ........................................................................................................... 9 section 2. mcu operating modes and address space ................................................ 17 2.1 overview............................................................................................................................... 17 2.2 mode descriptions................................................................................................................ 18 2.3 address space map .............................................................................................................. 19 2.3.1 access speed ........................................................................................................... 19 2.3.2 ios........................................................................................................................... 19 2.4 mode and system control registers (mdcr and syscr)................................................. 21 2.4.1 mode control register (mdcr) ?h'ffc5 ............................................................ 21 2.4.2 system control register (syscr) ?h'ffc4......................................................... 22 section 3. cpu ........................................................................................................................ 25 3.1 overview............................................................................................................................... 25 3.1.1 features.................................................................................................................... 25 3.2 register configuration.......................................................................................................... 26 3.2.1 general registers..................................................................................................... 26 3.2.2 control registers ..................................................................................................... 27 3.2.3 initial register values.............................................................................................. 28 3.3 addressing modes ................................................................................................................ 29 3.4 data formats......................................................................................................................... 31 3.4.1 data formats in general registers.......................................................................... 32 3.4.2 memory data formats............................................................................................. 33 3.5 instruction set ....................................................................................................................... 34 3.5.1 data transfer instructions ....................................................................................... 36 3.5.2 arithmetic operations ............................................................................................. 38 3.5.3 logic operations ..................................................................................................... 39 3.5.4 shift operations....................................................................................................... 39 3.5.5 bit manipulations .................................................................................................... 41 3.5.6 branching instructions............................................................................................. 47 3.5.7 system control instructions .................................................................................... 49 i 3.5.8 block data transfer instruction .............................................................................. 50 3.6 cpu states ............................................................................................................................ 51 3.6.1 program execution state ......................................................................................... 52 3.6.2 exception-handling state........................................................................................ 52 3.6.3 power-down state ................................................................................................... 53 3.7 access timing and bus cycle .............................................................................................. 53 3.7.1 access to on-chip memory (ram and rom) ...................................................... 53 3.7.2 access to on-chip register field and external devices ........................................ 55 section 4. exception handling ............................................................................................ 59 4.1 reset ..................................................................................................................................... 60 4.2 interrupts............................................................................................................................... 63 4.2.1 interrupt-related registers...................................................................................... 69 4.2.2 external interrupts ................................................................................................... 70 4.2.3 internal interrupts .................................................................................................... 71 4.2.4 interrupt response time.......................................................................................... 72 4.2.5 note on stack handling........................................................................................... 73 4.2.6 deferring of interrupts............................................................................................. 75 section 5. i/o ports ................................................................................................................ 77 5.1 overview............................................................................................................................... 77 5.2 port 1..................................................................................................................................... 78 5.3 port 2..................................................................................................................................... 81 5.4 port 3..................................................................................................................................... 84 5.5 port 4..................................................................................................................................... 88 5.6 port 5..................................................................................................................................... 91 5.7 port 6..................................................................................................................................... 96 5.8 port 7..................................................................................................................................... 102 5.9 port 8..................................................................................................................................... 104 5.10 port 9..................................................................................................................................... 114 section 6. 16-bit free-running timer .............................................................................. 123 6.1 overview............................................................................................................................... 123 6.1.1 features.................................................................................................................... 123 6.1.2 block diagram......................................................................................................... 123 6.1.3 input and output pins .............................................................................................. 125 6.1.4 register configuration ............................................................................................ 125 6.2 register descriptions............................................................................................................ 126 ii 6.2.1 free-running counter (frc) ?h'ff92.................................................................. 126 6.2.2 output compare registers a and b (ocra and ocrb) ?h'ff94....................... 127 6.2.3 input capture registers a to d (icra to icrd) h'ff98, h'ff9a, h'ff9c, h'ff9e ......................................................................... 127 6.2.4 timer interrupt enable register (tier) ?h'ff90 ................................................. 129 6.2.5 timer control/status register (tcsr) ?h'ff91 ................................................... 131 6.2.6 timer control register (tcr) ?h'ff96 ................................................................ 134 6.2.7 timer output compare control register (tocr) ?h'ff97.................................. 136 6.3 cpu interface ....................................................................................................................... 137 6.4 operation .............................................................................................................................. 139 6.4.1 frc incrementation timing.................................................................................... 139 6.4.2 output compare timing.......................................................................................... 141 6.4.3 input capture timing .............................................................................................. 142 6.4.4 setting of frc overflow flag (ovf)..................................................................... 145 6.5 interrupts............................................................................................................................... 146 6.6 sample application............................................................................................................... 146 6.7 application notes ................................................................................................................. 147 section 7. 8-bit timers ......................................................................................................... 153 7.1 overview............................................................................................................................... 153 7.1.1 features.................................................................................................................... 153 7.1.2 block diagram......................................................................................................... 153 7.1.3 input and output pins .............................................................................................. 154 7.1.4 register configuration ............................................................................................ 155 7.2 register descriptions............................................................................................................ 155 7.2.1 timer counter (tcnt) ?h'ffc8 (tmr0), h'ffd0 (tmr1) ............................... 155 7.2.2 time constant registers a and b (tcora and tcorb) h'ffca and h'ffcb (tmr0), h'ffd2 and h'ffd3 (tmr1) .............................. 156 7.2.3 timer control register (tcr) ?h'ffc8 (tmr0), h'ffd0 (tmr1) .................... 156 7.2.4 timer control/status register (tcsr) ?h'ffc9 (tmr0), h'ffd1 (tmr1) ....... 158 7.3 operation .............................................................................................................................. 160 7.3.1 tcnt incrementation timing................................................................................. 160 7.3.2 compare match timing........................................................................................... 161 7.3.3 external reset of tcnt .......................................................................................... 163 7.3.4 setting of tcsr overflow flag .............................................................................. 164 7.4 interrupts............................................................................................................................... 165 7.5 sample application............................................................................................................... 165 7.6 application notes ................................................................................................................. 166 iii section 8. pwm timers ........................................................................................................ 171 8.1 overview............................................................................................................................... 171 8.1.1 features.................................................................................................................... 171 8.1.2 block diagram......................................................................................................... 171 8.1.3 input and output pins .............................................................................................. 172 8.1.4 register configuration ............................................................................................ 172 8.2 register descriptions............................................................................................................ 172 8.2.1 timer counter (tcnt) ?h'ffa2 (pwm0), h'ffa6 (pwm1).............................. 172 8.2.2 duty register (dtr) ?h'ffa1 (pwm0), h'ffa5 (pwm1) ................................. 173 8.2.3 timer control register (tcr) ?h'ffa0 (pwm0), h'ffa4 (pwm1)................... 173 8.3 operation .............................................................................................................................. 175 8.3.1 timer incrementation .............................................................................................. 175 8.3.2 pwm operation....................................................................................................... 176 8.4 application notes ................................................................................................................. 177 section 9. serial communication interface ..................................................................... 179 9.1 overview............................................................................................................................... 179 9.1.1 features.................................................................................................................... 179 9.1.2 block diagram......................................................................................................... 180 9.1.3 input and output pins .............................................................................................. 180 9.1.4 register configuration ............................................................................................ 181 9.2 register descriptions............................................................................................................ 181 9.2.1 receive shift register (rsr) .................................................................................. 181 9.2.2 receive data register (rdr) ?h'ffdd................................................................ 182 9.2.3 transmit shift register (tsr)................................................................................. 182 9.2.4 transmit data register (tdr) ?h'ffdb............................................................... 182 9.2.5 serial mode register (smr) ?h'ffd8 .................................................................. 183 9.2.6 serial control register (scr) ?h'ffda ............................................................... 185 9.2.7 serial status register (ssr) ?h'ffdc .................................................................. 187 9.2.8 bit rate register (brr) ?h'ffd9 ......................................................................... 189 9.3 operation .............................................................................................................................. 193 9.3.1 overview ................................................................................................................. 193 9.3.2 asynchronous mode................................................................................................ 194 9.3.3 synchronous mode .................................................................................................. 198 9.4 interrupts............................................................................................................................... 202 9.5 application notes ................................................................................................................. 203 iv section 10. a/d converter ..................................................................................................... 207 10.1 overview............................................................................................................................... 207 10.1.1 features.................................................................................................................... 207 10.1.2 block diagram......................................................................................................... 208 10.1.3 input pins................................................................................................................. 209 10.1.4 register configuration ............................................................................................ 209 10.2 register descriptions............................................................................................................ 210 10.2.1 a/d data registers (addr) ?h'ffe0 to h'ffe6................................................. 210 10.2.2 a/d control/status register (adcsr) ?h'ffe8 .................................................. 210 10.2.3 a/d control register (adcr) ?h'ffea............................................................... 213 10.3 operation .............................................................................................................................. 213 10.3.1 single mode (scan = 0) ........................................................................................ 214 10.3.2 scan mode (scan = 1) .......................................................................................... 217 10.3.3 input sampling time and a/d conversion time.................................................... 220 10.3.4 external trigger input timing................................................................................. 222 10.4 interrupts............................................................................................................................... 223 section 11. dual-port ram (parallel communication interface) ............................... 225 11.1 overview............................................................................................................................... 225 11.1.1 features.................................................................................................................... 225 11.1.2 block diagram......................................................................................................... 226 11.1.3 input and output pins .............................................................................................. 227 11.1.4 register configuration ............................................................................................ 227 11.2 register descriptions............................................................................................................ 228 11.2.1 dual port ram enable bit (dpme)....................................................................... 228 11.2.2 parallel communication data register 0 (pcdr0) ?h'fff1 ................................ 230 11.2.3 parallel communication data registers 1 to 14 h'fff2 (pcdr1) to h'ffff (pcdr1-14).............................................................. 231 11.2.4 parallel communication control/status register (pccsr) ?h'fff0 ................... 231 11.3 usage .................................................................................................................................... 234 11.3.1 data transfer from master cpu to h8/300 cpu.................................................... 234 11.3.2 data transfer from h8/300 cpu to master cpu.................................................... 235 11.4 master-slave interconnections ............................................................................................. 237 section 12. ram ....................................................................................................................... 239 12.1 overview............................................................................................................................... 239 12.2 block diagram...................................................................................................................... 239 12.3 ram enable bit (rame) .................................................................................................... 239 v 12.4 operation .............................................................................................................................. 240 12.4.1 expanded modes (modes 1 and 2) .......................................................................... 240 12.4.2 single-chip mode (mode 3) ................................................................................... 240 section 13. rom ....................................................................................................................... 241 13.1 overview............................................................................................................................... 241 13.1.1 block diagram......................................................................................................... 242 13.2 prom mode......................................................................................................................... 242 13.2.1 prom mode setup ................................................................................................. 242 13.2.2 socket adapter pin assignments and memory map............................................... 243 13.3 programming ........................................................................................................................ 245 13.3.1 writing and verifying .............................................................................................. 245 13.3.2 notes on writing...................................................................................................... 249 13.3.3 reliability of written data ...................................................................................... 249 13.3.4 erasing of data ........................................................................................................ 250 13.4 handling of windowed packages......................................................................................... 250 section 14. power-down state .............................................................................................. 253 14.1 overview............................................................................................................................... 253 14.2 system control register: power-down control bits ........................................................... 254 14.3 sleep mode ........................................................................................................................... 255 14.3.1 transition to sleep mode......................................................................................... 256 14.3.2 exit from sleep mode ............................................................................................. 256 14.4 software standby mode........................................................................................................ 256 14.4.1 transition to software standby mode..................................................................... 257 14.4.2 exit from software standby mode.......................................................................... 257 14.4.3 sample application of software standby mode ..................................................... 257 14.4.4 application notes .................................................................................................... 258 14.5 hardware standby mode ...................................................................................................... 259 14.5.1 transition to hardware standby mode.................................................................... 259 14.5.2 recovery from hardware standby mode................................................................ 259 14.5.3 timing relationships............................................................................................... 260 section 15. e-clock interface ................................................................................................ 261 15.1 overview............................................................................................................................... 261 section 16. clock pulse generator ....................................................................................... 265 16.1 overview............................................................................................................................... 265 vi 16.1.1 block diagram......................................................................................................... 265 16.2 oscillator circuit................................................................................................................... 265 16.3 system clock divider........................................................................................................... 268 section 17. electrical specifications .................................................................................... 269 17.1 absolute maximum ratings ................................................................................................. 269 17.2 electrical characteristics ...................................................................................................... 269 17.2.1 dc characteristics................................................................................................... 269 17.2.2 ac characteristics................................................................................................... 273 17.2.3 a/d converter characteristics................................................................................. 277 17.3 mcu operational timing..................................................................................................... 278 17.3.1 bus timing .............................................................................................................. 278 17.3.2 control signal timing ............................................................................................. 280 17.3.3 16-bit free-running timer timing ........................................................................ 283 17.3.4 8-bit timer timing.................................................................................................. 284 17.3.5 pulse width modulation timer timing................................................................... 285 17.3.6 serial communication interface timing ................................................................. 285 17.3.7 i/o port timing........................................................................................................ 286 17.3.8 dual-port ram timing........................................................................................... 287 appendices appendix a. cpu instruction set ...................................................................................... 289 a.1 instruction set list................................................................................................................ 289 a.2 operation code map............................................................................................................. 296 a.3 number of states required for execution............................................................................ 298 appendix b. register field ................................................................................................. 304 b.1 register addresses and bit names....................................................................................... 304 b.2 register descriptions............................................................................................................ 308 appendix c. pin states ......................................................................................................... 337 c.1 pin states in each mode ....................................................................................................... 337 appendix d. timing of transition to and recovery from hardware standby mode ................................................................................................ 339 appendix e. package dimensions .................................................................................... 340 vii table table 1-1 product lineup ...................................................................................................... 5 table 1-2 pin assignments in each operating mode (1)...................................................... 9 table 1-3 pin functions (1) ................................................................................................... 12 table 2-1 operating modes ................................................................................................... 17 table 2-2 mode and system control registers..................................................................... 21 table 3-1 instruction classification....................................................................................... 34 table 3-2 data transfer instructions ..................................................................................... 36 table 3-3 arithmetic instructions.......................................................................................... 38 table 3-4 logic operation instructions................................................................................. 39 table 3-5 shift instructions ................................................................................................... 39 table 3-6 bit-manipulation instruction (1) ........................................................................... 41 table 3-7 branching instructions .......................................................................................... 47 table 3-8 system control instructions .................................................................................. 49 table 3-9 block data transfer instruction/eeprom write operation................................ 50 table 4-1 reset and interrupt exceptions ............................................................................. 59 table 4-2 interrupts ............................................................................................................... 64 table 4-3 registers read by interrupt controller ................................................................. 69 table 4-4 number of states before interrupt service............................................................ 73 table 5-1 auxiliary functions of input/output ports............................................................ 78 table 5-2 functions of port 1 ................................................................................................ 78 table 5-3 port 1 registers ..................................................................................................... 79 table 5-4 functions of port 2 ................................................................................................ 81 table 5-5 port 2 registers ..................................................................................................... 82 table 5-6 functions of port 3 ................................................................................................ 84 table 5-7 port 3 registers ..................................................................................................... 85 table 5-8 port 4 pin functions (mode 1 to 3) ....................................................................... 88 table 5-9 port 4 registers ..................................................................................................... 88 table 5-10 port 5 pin functions (mode 1 to 3) ....................................................................... 91 table 5-11 port 5 registers ..................................................................................................... 92 table 5-12 port 6 pin functions .............................................................................................. 96 table 5-13 port 6 registers ..................................................................................................... 97 table 5-14 port 7 pin functions (mode 1 to 3) ....................................................................... 103 viii table 5-15 port 7 registers ..................................................................................................... 103 table 5-16 port 8 pin functions .............................................................................................. 104 table 5-17 port 8 registers ..................................................................................................... 104 table 5-18 port 9 pin functions .............................................................................................. 114 table 5-19 port 9 registers ..................................................................................................... 114 table 6-1 input and output pins of free-running timer module ........................................ 125 table 6-2 register configuration .......................................................................................... 125 table 6-3 free-running timer interrupts ............................................................................. 146 table 6-4 effect of changing internal clock sources........................................................... 150 table 7-1 input and output pins of 8-bit timer ................................................................... 154 table 7-2 8-bit timer registers ............................................................................................ 155 table 7-3 8-bit timer interrupts ........................................................................................... 165 table 7-4 priority of timer output........................................................................................ 168 table 7-5 effect of changing internal clock sources........................................................... 169 table 8-1 output pins of pwm timer module..................................................................... 172 table 8-2 pwm timer registers........................................................................................... 172 table 8-3 pwm timer parameters for 10mhz system clock.............................................. 175 table 9-1 sci input/output pins ........................................................................................... 180 table 9-2 sci registers......................................................................................................... 181 table 9-3 examples of brr settings in asynchronous mode (1)........................................ 189 table 9-4 examples of brr settings in synchronous mode................................................ 192 table 9-5 communication formats used by sci.................................................................. 193 table 9-6 sci clock source selection .................................................................................. 193 table 9-7 data formats in asynchronous mode................................................................... 195 table 9-8 receive errors ....................................................................................................... 198 table 9-9 sci interrupts ........................................................................................................ 203 table 9-10 ssr bit states and data transfer when multiple receive errors occur............. 204 table 10-1 a/d input pins....................................................................................................... 209 table 10-2 a/d registers ........................................................................................................ 209 table 10-3 assignment of data registers to analog input channels..................................... 210 table 10-4 (a) a/d conversion time (single mode) ................................................................... 222 table 10-4 (b) a/d conversion time (scan mode) ..................................................................... 222 ix table 11-1 dual-port ram input and output pins................................................................. 227 table 11-2 dual-port ram register configuration ............................................................... 227 table 12-1 system control register........................................................................................ 240 table 13-1 on-chip rom usage in each mcu mode .......................................................... 241 table 13-2 selection of prom mode ..................................................................................... 242 table 13-3 recommended socket adapters............................................................................ 243 table 13-4 selection of sub-modes in prom mode ............................................................. 245 table 13-5 dc characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, v ss = 0v, ta=25?c 5?c) ..................................................................................... 247 table 13-6 ac characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, ta=25?c 5?c) ...................................................................................................... 247 table 13-7 erasing conditions ................................................................................................ 250 table 13-8 recommended socket for mounting 84-pin lcc package.................................. 251 table 14-1 power-down state................................................................................................. 253 table 14-2 system control register........................................................................................ 254 table 14-3 times set by standby timer select bits (unit: ms) ............................................. 255 table 16-1 external crystal parameters .................................................................................. 266 table 17-1 absolute maximum ratings.................................................................................. 269 table 17-2 dc characteristics................................................................................................. 270 table 17-3 allowable output current sink values................................................................. 272 table 17-4 bus timing ............................................................................................................ 273 table 17-5 control signal timing........................................................................................... 274 table 17-6 timing conditions of on-chip supporting modules............................................ 274 table 17-7 a/d converter characteristics .............................................................................. 277 table a-1 instruction set ....................................................................................................... 290 table a-2 operation code map ............................................................................................. 297 table a-3 number of states taken by each cycle in instruction execution ........................ 298 table a-4 number of cycles in each instruction .................................................................. 299 table c-1 pin states ............................................................................................................... 337 x figure figure 1-1 block diagram ...................................................................................................... 2 figure 1-2 pin arrangement (fp-80a, top view) ................................................................. 6 figure 1-3 pin arrangement (cp-84, top view) .................................................................... 7 figure 1-4 pin arrangement (cg-84, top view) ................................................................... 8 figure 2-1 address space map............................................................................................... 20 figure 3-1 cpu registers ....................................................................................................... 26 figure 3-2 stack pointer ......................................................................................................... 27 figure 3-3 register data formats........................................................................................... 32 figure 3-4 memory data formats .......................................................................................... 33 figure 3-5 data transfer instruction codes............................................................................ 37 figure 3-6 arithmetic, logic, and shift instruction codes .................................................... 40 figure 3-7 bit manipulation instruction codes ...................................................................... 46 figure 3-8 branching instruction codes................................................................................. 48 figure 3-9 system control instruction codes......................................................................... 50 figure 3-10 block data transfer instruction/eeprom write operation code ...................... 51 figure 3-11 operating states .................................................................................................... 51 figure 3-12 state transitions .................................................................................................... 52 figure 3-13 on-chip memory access cycle ........................................................................... 54 figure 3-14 pin states during on-chip memory access cycle ............................................... 54 figure 3-15 on-chip register field access cycle................................................................... 55 figure 3-16 pin states during on-chip register field access cycle ...................................... 56 figure 3-17(a) external device access timing (read) ................................................................. 56 figure 3-17(b) external device access timing (write) ................................................................ 57 figure 4-1 reset sequence (mode 2 or 3, reset routine in on-chip rom)......................... 61 figure 4-2 reset sequence (mode 1)...................................................................................... 62 figure 4-3 block diagram of interrupt controller.................................................................. 66 figure 4-4 hardware interrupt-handling sequence................................................................ 67 figure 4-5 timing of interrupt sequence................................................................................ 68 figure 4-6 usage of stack in interrupt handling.................................................................... 74 figure 4-7 example of damage caused by setting an odd address in r7 ........................... 75 figure 4-8 example of deferred interrupt .............................................................................. 76 figure 5-1 port 1 schematic diagram..................................................................................... 81 xi figure 5-2 port 2 schematic diagram..................................................................................... 84 figure 5-3 port 3 schematic diagram..................................................................................... 87 figure 5-4 port 4 schematic diagram (pins p4 0 , p4 2 , p4 3 , and p4 5 ) ..................................... 90 figure 5-5 port 4 schematic diagram (pins p4 1 , p4 4 , p4 6 , and p4 7 ) ..................................... 91 figure 5-6 port 5 schematic diagram (pin p5 0 )..................................................................... 94 figure 5-7 port 5 schematic diagram (pin p5 1 )..................................................................... 95 figure 5-8 port 5 schematic diagram (pin p5 2 )..................................................................... 96 figure 5-9 port 6 schematic diagram (pins p6 0 , p6 2 , p6 3 , p6 4 , and p6 5 ).............................. 99 figure 5-10 port 6 schematic diagram (pin p6 1 )..................................................................... 100 figure 5-11 port 6 schematic diagram (pin p6 6 )..................................................................... 101 figure 5-12 port 6 schematic diagram (pin p6 7 )..................................................................... 102 figure 5-13 port 7 schematic diagram..................................................................................... 103 figure 5-14 port 8 schematic diagram (pin p8 0 )..................................................................... 108 figure 5-15 port 8 schematic diagram (pin p8 1 )..................................................................... 109 figure 5-16 port 8 schematic diagram (pins p8 2 and p8 3 )...................................................... 110 figure 5-17 port 8 schematic diagram (pin p8 4 )..................................................................... 111 figure 5-18 port 8 schematic diagram (pin p8 5 )..................................................................... 112 figure 5-19 port 8 schematic diagram (pin p8 6 )..................................................................... 113 figure 5-20 port 9 schematic diagram (pin p9 0 )..................................................................... 117 figure 5-21 port 9 schematic diagram (pins p9 1 to p9 2 ) ........................................................ 118 figure 5-22 port 9 schematic diagram (pins p9 3 and p9 4 )...................................................... 119 figure 5-23 port 9 schematic diagram (pin p9 5 )..................................................................... 120 figure 5-24 port 9 schematic diagram (pin p9 6 )..................................................................... 121 figure 5-25 port 9 schematic diagram (pin p9 7 )..................................................................... 122 figure 6-1 block diagram of 16-bit free-running timer..................................................... 124 figure 6-2 input capture buffering ........................................................................................ 128 figure 6-3 minimum input capture pulse width ................................................................... 128 figure 6-4 (a) write access to frc (when cpu writes h'aa55) ............................................. 138 figure 6-4 (b) read access to frc (when frc contains h'aa55) .......................................... 139 figure 6-5 increment timing for internal clock source ........................................................ 140 figure 6-6 increment timing for external clock source ....................................................... 140 figure 6-7 minimum external clock pulse width ................................................................. 140 figure 6-8 setting of output compare flags.......................................................................... 141 figure 6-9 clearing of output compare flag......................................................................... 141 figure 6-10 timing of output compare a ............................................................................... 142 figure 6-11 clearing of frc by compare-match a ................................................................ 142 figure 6-12 input capture timing (usual case) ...................................................................... 143 xii figure 6-13 input capture timing (1-state delay)................................................................... 143 figure 6-14 input capture timing (1-state delay, buffer mode) ............................................ 143 figure 6-15 buffered input capture with both edges selected ............................................... 144 figure 6-16 setting of input capture flag ................................................................................ 144 figure 6-17 clearing of input capture flag.............................................................................. 145 figure 6-18 setting of overflow flag (ovf) ........................................................................... 145 figure 6-19 clearing of overflow flag .................................................................................... 145 figure 6-20 square-wave output (example) ........................................................................... 146 figure 6-21 frc write-clear contention................................................................................. 147 figure 6-22 frc write-increment contention ......................................................................... 148 figure 6-23 contention between ocr write and compare-match.......................................... 149 figure 7-1 block diagram of 8-bit timer .............................................................................. 154 figure 7-2 count timing for internal clock input ................................................................. 160 figure 7-3 count timing for external clock input ................................................................ 161 figure 7-4 minimum external clock pulse widths................................................................ 161 figure 7-5 setting of compare-match flags .......................................................................... 162 figure 7-6 clearing of compare-match flags........................................................................ 162 figure 7-7 timing of timer output ........................................................................................ 163 figure 7-8 timing of compare-match clear .......................................................................... 163 figure 7-9 timing of external reset ...................................................................................... 164 figure 7-10 setting of overflow flag (ovf) ........................................................................... 164 figure 7-11 clearing of overflow flag .................................................................................... 165 figure 7-12 example of pulse output....................................................................................... 166 figure 7-13 tcnt write-clear contention.............................................................................. 166 figure 7-14 tcnt write-increment contention ...................................................................... 167 figure 7-15 contention between tcor write and compare-match ....................................... 168 figure 8-1 block diagram of pwm timer............................................................................. 171 figure 8-2 tcnt increment timing....................................................................................... 175 figure 8-3 pwm timing......................................................................................................... 176 figure 9-1 block diagram of serial communication interface.............................................. 180 figure 9-2 data format in asynchronous mode .................................................................... 194 figure 9-3 phase relationship between clock output and transmit data ............................ 195 figure 9-4 data format in synchronous mode ...................................................................... 199 figure 9-5 timing of interrupt signal..................................................................................... 203 figure 9-6 sampling timing (asynchronous mode).............................................................. 205 xiii figure 10-1 block diagram of a/d converter ......................................................................... 208 figure 10-2 the response of the a/d converter ..................................................................... 214 figure 10-3 a/d operation in single mode (when channel 1 is selected)............................. 216 figure 10-4 a/d operation in scan mode (when channel 0 to 2 are selected)...................... 219 figure 10-5 a/d conversion timing........................................................................................ 221 figure 10-6 external trigger input timing .............................................................................. 222 figure 11-1 block diagram of dual-port ram ....................................................................... 226 figure 11-2 parallel communication data register 0 .............................................................. 230 figure 11-3 dual-port ram timing chart .............................................................................. 236 figure 11-4 interconnection to h8/532 (example)................................................................... 237 figure 12-1 block diagram of on-chip ram......................................................................... 239 figure 13-1 block diagram of on-chip rom......................................................................... 242 figure 13-2 socket adapter pin assignments .......................................................................... 244 figure 13-3 memory map in prom mode .............................................................................. 245 figure 13-4 high-speed programming flowchart.................................................................... 246 figure 13-5 prom write/verify timing.................................................................................. 248 figure 13-6 recommended screening procedure..................................................................... 249 figure 14-1 software standby mode (when) nmi timing ...................................................... 258 figure 14-2 hardware standby mode timing .......................................................................... 260 figure 15-1 execution cycle of instruction synchronized with e clock in expanded modes (maximum synchronization delay)......................................... 262 figure 15-2 execution cycle of instruction synchronized with e clock in expanded modes (minimum synchronization delay).......................................... 263 figure 16-1 block diagram of clock pulse generator............................................................. 265 figure 16-2 connection of crystal oscillator (example)......................................................... 266 figure 16-3 equivalent circuit of external crystal .................................................................. 266 figure 16-4 notes on board design around external crystal .................................................. 267 figure 16-5 external clock input (example) ........................................................................... 267 figure 16-6 phase relationship of system clock and e clock................................................ 268 figure 17-1 example of circuit for driving a darlington pair................................................. 272 figure 17-2 example of circuit for driving a led.................................................................. 272 xiv figure 17-3 output load circuit .............................................................................................. 277 figure 17-4 basic bus cycle (without wait states) in expanded modes................................ 278 figure 17-5 basic bus cycle (without 1 wait states) in expanded modes............................. 279 figure 17-6 e clock bus cycle ................................................................................................ 280 figure 17-7 reset input timing................................................................................................ 280 figure 17-8 interrupt input timing........................................................................................... 281 figure 17-9 clock settling timing ........................................................................................... 282 figure 17-10 clock settling timing for recovery from software standby mode..................... 283 figure 17-11 free-running timer input/output timing............................................................ 283 figure 17-12 external clock input timing for free-running timer ......................................... 284 figure 17-13 8-bit timer output timing ................................................................................... 284 figure 17-14 8-bit timer clock input timing ........................................................................... 284 figure 17-15 8-bit timer reset input timing ............................................................................ 285 figure 17-16 pwm timer output timing.................................................................................. 285 figure 17-17 sci input/output timing (synchronous mode) ................................................... 285 figure 17-18 sci input clock timing ........................................................................................ 286 figure 17-19 i/o port input/output timing................................................................................ 286 figure 17-20 dual-port ram read timing ............................................................................... 287 figure 17-21 dual-port ram write timing .............................................................................. 288 appendix e-1 package dimensions (cg-84)............................................................................... 340 appendix e-2 package dimensions (cp-84)................................................................................ 340 appendix e-3 package dimensions (fp-80a) ............................................................................. 341 xv section 1. overview the h8/330 is a single-chip microcomputer with an h8/300 cpu core and a complement of on- chip supporting modules. a variety of system functions are integrated onto the h8/330 chip. the h8/300 cpu is a high-speed hitachi-original processor with an architecture featuring powerful bit-manipulation instructions, ideally suited for realtime control applications. the on-chip supporting modules include 16k bytes of rom, 512 bytes of ram, a 16-bit free-running timer, two 8-bit timers, two pwm timers, a serial communication interface, an a/d converter, dual-port ram, and i/o ports. the h8/330 can operate in single-chip mode or in two expanded modes, depending on the memory requirements of the application. the operating mode is referred to in this manual as the mcu mode (mcu: microcomputer unit). the h8/330 is available in a masked rom version, in an electrically programmable rom version that can be programmed at the user site, or in a version with no rom. the no-rom version can be used only in mode 1. section 1.1 shows a block diagram of the h8/330. section 1.2 describes the main features of the blocks. section 1.3 shows the pin layout and describes the pin functions. 1 1.1 block diagram figure 1-1 shows a block diagram of the h8/330 chip. figure 1-1. block diagram port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 cpu h8/300 data bus (high) address bus dual-port ram 8-bit a/d converter (8 channels) port 1 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 p9 0 /irq 2 /adtrg p9 1 /irq 1 p9 2 /irq 0 p9 3 /cs/rd p9 4 /oe/wr p9 5 /rdy/as p9 6 / p9 7 /we/wait p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 p6 0 /ftci p6 1 /ftoa p6 2 /ftia p6 3 /ftib p6 4 /ftic p6 5 /ftid p6 6 /ftob/irq 6 p6 7 /irq 7 p3 0 /ddb 0 /d 0 p3 1 /ddb 1 /d 1 p3 2 /ddb 2 /d 2 p3 3 /ddb 3 /d 3 p3 4 /ddb 4 /d 4 p3 5 /ddb 5 /d 5 p3 6 /ddb 6 /d 6 p3 7 /ddb 7 /d 7 p8 0 /rs 0 /e p8 1 /rs 1 /ios p8 2 /rs 2 p8 3 /rs 3 p8 4 /ctxd/irq 3 p8 5 /crxd/irq 4 p8 6 /csck/irq 5 xtal extal stby v cc v cc v ss v ss v ss v ss v ss v ss v ss p4 0 /tmci 0 p4 1 /tmo 0 p4 2 /tmri 0 p4 3 /tmci 1 p4 4 /tmo 1 p4 5 /tmri 1 p4 6 /pw 0 p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 p7 4 /an 4 p7 5 /an 5 p7 6 /an 6 av cc av ss p5 0 /atxd p5 1 /arxd p5 2 /asck clock pulse gener- ator serial communication (8 channels) 16-bit free-running timer 8-bit timer (2 channels) pwm timer (2 channels) * * cp-84, cg-84 prom (or masked rom) 16k bytes ram 512 bytes data bus (low) 2 1.2 descriptions of blocks cpu: the cpu has a high-speed-oriented architecture in which operands are located in general registers. two-way general register configuration - eight 16-bit registers, or - sixteen 8-bit registers streamlined instruction set - instruction length: 2 or 4 bytes - register-register arithmetic, logic, and shift operations, including: - 8 8-bit multiply - 16 8-bit divide - extensive bit-manipulation instructions, featuring: - bit accumulator - register-indirect specification of bit positions - maximum clock rate: 10mhz - register-register add or subtract: 0.2 s - register-register multiply or divide: 1.4 s rom: the 16k-byte on-chip rom is accessed in two states via a 16-bit bus. three versions are available: masked rom electrically programmable rom, programmable with a standard prom writer no rom ram: the 512-byte on-chip ram is accessed in two states via a 16-bit bus. ram contents are held in the power-down state. dual-port ram: in single-chip mode, the 15 bytes of dual-port memory can be accessed by both the on-chip cpu and an external cpu for convenient parallel data transfer in master-slave systems. serial communication interface: the single serial i/o channel offers: synchronous or asynchronous communication separate input/output pins for the synchronous and asynchronous modes an on-chip baud rate generator supporting up to megabit-per-second speeds serial clock input or output 3 a/d converter: a/d conversion can be performed in single or scan mode. eight-bit resolution eight input channels; selection of single mode or scan mode conversion can be started by an external trigger signal sample-and-hold i/o ports: pins not used for other functions are available for general-purpose input and output. i/o is memory-mapped, with the cpu reading and writing the port registers in three states via an 8- bit internal bus. 58 input/output pins (including 16 pins with led driving capability) 8 input-only pins interrupts: with a 10mhz clock rate, interrupt response times are on the order of 2 or 3 s (when the vector table and stack are located in on-chip memory). 9 external interrupts: nmi and irq 0 to irq 7 19 internal interrupts free-running timer: the time base is a 16-bit free-running counter that can be internally or externally clocked. applications range from programmable pulse output to counting or timing of external events. two independent, comparator-controlled outputs four input capture channels input capture buffering 8-bit timers: two independent 8-bit timers support applications such as programmable pulse output and external event counting. internal or external clocking output controlled by values in two compare registers pwm timers: two independent timers are provided for pulse-width modulated output. duty cycles from 0 to 100% can be selected with 1/250 resolution. power-down state: in the three power-down modes some or all chip functions are halted but memory contents are retained. sleep mode: cpu halts to save power while waiting for an interrupt software standby mode: entire chip halts to save power while waiting for an external interrupt hardware standby mode: totally shut down, but on-chip ram contents are held 4 clock pulse generator: the h8/330 can generate its system clock from a crystal oscillator, or can input an external clock signal. e-clock interface: an e clock can be output for interfacing to peripheral devices. mcu modes: the h8/330 has three operating modes: mode 1: expanded mode, on-chip rom disabled mode 2: expanded mode, on-chip rom enabled mode 3: single-chip mode product lineup: a selection is offered of 80- or 84-pin packages with prom or masked rom. see table 1-1. the windowed prom version is uv-erasable. table 1-1. product lineup product code package on-chip rom hd6473308f 80-pin qfp (fp-80a) hd6473308cp 84-pin plcc (cp-84) prom hd6473308cg 84-pin windowed lcc (cg-84) hd6433308f 80-pin qfp (fp-80a) masked rom hd6433308cp 84-pin plcc (cp-84) HD6413308cp 84-pin plcc (cp-84) no rom HD6413308f 80-pin qfp (fp-80a) 5 1.3 pin assignments and functions 1.3.1 pin arrangement figure 1-2 shows the pin arrangement of the fp-80a package. figure 1-3 shows the pin arrangement of the cp-84 package. figure 1-4 shows the pin arrangement of the cg-84 package. figure 1-2. pin arrangement (fp-80a, top view) 68 67 64 63 62 61 80 79 78 77 76 75 74 73 72 71 70 69 66 65 13 14 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 15 16 48 47 44 43 42 41 60 59 58 57 56 55 54 53 52 51 50 49 46 45 33 34 37 38 39 40 21 22 23 24 25 26 27 28 29 30 31 32 35 36 res xtal extal md 1 md 0 nmi stby v cc p5 2 /asck p5 1 /arxd p5 0 /atxd v ss p9 7 /we/wait p9 6 / p9 5 /rdy/as p9 4 /oe/wr p9 3 /cs/rd p9 2 /irq 0 p9 1 /irq 1 p9 0 /irq 2 /adtrg p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 p4 4 /tmo 1 p4 3 /tmci 1 p4 2 /tmri 1 v ss p3 7 /ddb 7 /d 7 p3 6 /ddb 6 /d 6 p3 5 /ddb 5 /d 5 p3 4 /ddb 4 /d 4 p3 3 /ddb 3 /d 3 p3 2 /ddb 2 /d 2 p3 1 /ddb 1 /d 1 p3 0 /ddb 0 /d 0 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p6 0 /ftci p6 1 /ftoa p6 2 /ftia p6 3 /ftib p6 4 /ftic p6 5 /ftid p6 6 /ftob/irq 6 p6 7 /irq 7 av cc p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 6 figure 1-3. pin arrangement (cp-84, top view) 24 25 28 29 30 31 12 13 14 15 16 17 18 19 20 21 22 23 26 27 32 45 46 49 50 51 52 33 34 35 36 37 38 39 40 41 42 43 44 47 48 53 62 61 58 57 56 55 74 73 72 71 70 69 68 67 66 65 64 63 60 59 54 83 82 11 10 9 8 7 6 5 4 3 2 1 84 79 78 77 76 81 80 75 res xtal extal md 1 md 0 nmi stby v cc p5 2 /asck p5 1 /arxd p5 0 /atxd v ss v ss p9 7 /we/wait p9 6 / p9 5 /rdy/as p9 4 /oe/wr p9 3 /cs/rd p9 2 /irq 0 p9 1 /irq 1 p9 0 /irq 2 /adtrg p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 v ss p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 p4 4 /tmo 1 p4 3 /tmci 1 p4 2 /tmri 0 v ss p3 7 /ddb 7 /d 7 v ss p3 6 /ddb 6 /d 6 p3 5 /ddb 5 /d 5 p3 4 /ddb 4 /d 4 p3 3 /ddb 3 /d 3 p3 2 /ddb 2 /d 2 p3 1 /ddb 1 /d 1 p3 0 /ddb 0 /d 0 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p6 0 /ftci p6 1 /ftoa p6 2 /ftia p6 3 /ftib p6 4 /ftic p6 5 /ftid p6 6 /ftob/irq 6 p6 7 /irq 7 v ss av cc p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 7 figure 1-4. pin arrangement (cg-84, top view) 24 25 28 29 30 31 12 13 14 15 16 17 18 19 20 21 22 23 26 27 32 45 46 49 50 51 52 33 34 35 36 37 38 39 40 41 42 43 44 47 48 53 62 61 58 57 56 55 74 73 72 71 70 69 68 67 66 65 64 63 60 59 54 83 82 11 10 9 8 7 6 5 4 3 2 1 84 79 78 77 76 81 80 75 res xtal extal md 1 md 0 nmi stby v cc p5 2 /asck p5 1 /arxd p5 0 /atxd v ss v ss p9 7 /we/wait p9 6 / p9 5 /rdy/as p9 4 /oe/wr p9 3 /cs/rd p9 2 /irq 0 p9 1 /irq 1 p9 0 /irq 2 /adtrg p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 v ss p2 0 /a 8 p2 1 /a 9 p2 2 /a 10 p2 3 /a 11 p2 4 /a 12 v ss p2 5 /a 13 p2 6 /a 14 p2 7 /a 15 v cc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 p4 4 /tmo 1 p4 3 /tmci 1 p4 2 /tmri 0 p6 0 /ftci p6 1 /ftoa p6 2 /ftia p6 3 /ftib p6 4 /ftic p6 5 /ftid p6 6 /ftob/irq 6 p6 7 /irq 7 v ss av cc p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 v ss p3 7 /ddb 7 /d 7 v ss p3 6 /ddb 6 /d 6 p3 5 /ddb 5 /d 5 p3 4 /ddb 4 /d 4 p3 3 /ddb 3 /d 3 p3 2 /ddb 2 /d 2 p3 1 /ddb 1 /d 1 p3 0 /ddb 0 /d 0 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 8 1.3.2 pin functions (1) pin assignments in each operating mode: table 1-2 lists the assignments of the pins of the fp-80a, cp-84, and cg-84 packages in each operating mode. the prom mode is a non-operating mode used for programming the on-chip rom. see section 13, ?om?for details. table 1-2. pin assignments in each operating mode (1) note: pins marked nc should be left unconnected. *input port only pin no. single-chip mode (mode 3) expanded modes cp-84 fp dpram dpram (modes 1 and 2) prom cg-84 -80a disabled enabled mode 1 71 p3 6 ddb 6 d 6 eo 6 2 v ss v ss v ss v ss 3 72 p3 7 ddb 7 d 7 eo 7 4 73 v ss v ss v ss v ss 5 74 p8 0 rs 0 p8 0* / e v cc 6 75 p8 1 rs 1 p8 1* /ios v cc 7 76 p8 2 rs 2 p8 2 nc 8 77 p8 3 rs 3 p8 3 nc 9 78 p8 4 / ctxd /irq 3 p8 4 / ctxd /irq 3 p8 4 / ctxd /irq 3 nc 10 79 p8 5 / crxd /irq 4 p8 5 / crxd /irq 4 p8 5 / crxd /irq 4 nc 11 80 p8 6 / csck /irq 5 p8 6 / csck /irq 5 p8 6 / csck /irq 5 nc 12 1 res res res v pp 13 2 xtal xtal xtal nc 14 3 extal extal extal nc 15 4 md 1 md 1 md 1 v ss 16 5 md 0 md 0 md 0 v ss 17 6 nmi nmi nmi ea 9 18 7 stby stby stby v ss 19 8 v cc v cc v cc v cc 20 9 p5 2 / asck p5 2 / asck p5 2 / asck nc 21 10 p5 1 / arxd p5 1 / arxd p5 1 / arxd nc 22 11 p5 0 / atxd p5 0 / atxd p5 0 / atxd nc 9 table 1-2. pin assignments in each operating mode (2) note: pins marked nc should be left unconnected. *input port only pin no. single-chip mode (mode 3) expanded modes cp-84 fp dpram dpram (modes 1 and 2) prom cg-84 -80a disabled enabled mode 23 12 v ss v ss v ss v ss 24 v ss v ss v ss v ss 25 13 p9 7 we wait nc 26 14 p9 6 * / p9 6 * / nc 27 15 p9 5 rdy as nc 28 16 p9 4 oe wr nc 29 17 p9 3 cs rd nc 30 18 p9 2 / irq 0 p9 2 / irq 0 p9 2 / irq 0 nc 31 19 p9 1 / irq 1 p9 1 / irq 1 p9 1 / irq 1 nc 32 20 p9 0 / adtrg / irq 2 p9 0 / adtrg / irq 2 p9 0 / adtrg / irq 2 nc 33 21 p6 0 / ftci p6 0 / ftci p6 0 / ftci nc 34 22 p6 1 / ftoa p6 1 / ftoa p6 1 / ftoa nc 35 23 p6 2 / ftia p6 2 / ftia p6 2 / ftia nc 36 24 p6 3 / ftib p6 3 / ftib p6 3 / ftib nc 37 25 p6 4 / ftic p6 4 / ftic p6 4 / ftic nc 38 26 p6 5 / ftid p6 5 / ftid p6 5 / ftid nc 39 27 p6 6 / ftob /irq 6 p6 6 / ftob /irq 6 p6 6 / ftob /irq 6 nc 40 28 p6 7 /irq 7 p6 7 /irq 7 p6 7 /irq 7 nc 41 v ss v ss v ss v ss 42 29 av cc av cc av cc v cc 43 30 p7 0 / an 0 p7 0 / an 0 p7 0 / an 0 nc 44 31 p7 1 / an 1 p7 1 / an 1 p7 1 / an 1 nc 45 32 p7 2 / an 2 p7 2 / an 2 p7 2 / an 2 nc 46 33 p7 3 / an 3 p7 3 / an 3 p7 3 / an 3 nc 47 34 p7 4 / an 4 p7 4 / an 4 p7 4 / an 4 nc 48 35 p7 5 / an 5 p7 5 / an 5 p7 5 / an 5 nc 49 36 p7 6 / an 6 p7 6 / an 6 p7 6 / an 6 nc 50 37 p7 7 / an 7 p7 7 / an 7 p7 7 / an 7 nc 51 38 av ss av ss av ss v ss 52 39 p4 0 / tmci 0 p4 0 / tmci 0 p4 0 / tmci 0 nc 53 40 p4 1 / tmo 0 p4 1 / tmo 0 p4 1 / tmo 0 nc 10 table 1-2. pin assignments in each operating mode (3) note: pins marked nc should be left unconnected. *input port only pin no. single-chip mode (mode 3) expanded modes cp-84 fp dpram dpram (modes 1 and 2) prom cg-84 -80a disabled enabled mode 54 41 p4 2 / tmri 0 p4 2 / tmri 0 p4 2 / tmri 0 nc 55 42 p4 3 / tmci 1 p4 3 / tmci 1 p4 3 / tmci 1 nc 56 43 p4 4 / tmo 1 p4 4 / tmo 1 p4 4 / tmo 1 nc 57 44 p4 5 / tmri 1 p4 5 / tmri 1 p4 5 / tmri 1 nc 58 45 p4 6 / pw 0 p4 6 / pw 0 p4 6 / pw 0 nc 59 46 p4 7 / pw 1 p4 7 / pw 1 p4 7 / pw 1 nc 60 47 v cc v cc v cc v cc 61 48 p2 7 p2 7 a 15 p2 7* / a 15 ce 62 49 p2 6 p2 6 a 14 p2 6* / a 14 ea 14 63 50 p2 5 p2 5 a 13 p2 5* / a 13 ea 13 64 v ss v ss v ss v ss v ss 65 51 p2 4 p2 4 a 12 p2 4* / a 12 ea 12 66 52 p2 3 p2 3 a 11 p2 3* / a 11 ea 11 67 53 p2 2 p2 2 a 10 p2 2* / a 10 ea 10 68 54 p2 1 p2 1 a 9 p2 1* / a 9 oe 69 55 p2 0 p2 0 a 8 p2 0* / a 8 ea 8 70 56 v ss v ss v ss v ss v ss 71 57 p1 7 p1 7 a 7 p1 7* / a 7 ea 7 72 58 p1 6 p1 6 a 6 p1 6* / a 6 ea 6 73 59 p1 5 p1 5 a 5 p1 5* / a 5 ea 5 74 60 p1 4 p1 4 a 4 p1 4* / a 4 ea 4 75 61 p1 3 p1 3 a 3 p1 3* / a 3 ea 3 76 62 p1 2 p1 2 a 2 p1 2* / a 2 ea 2 77 63 p1 1 p1 1 a 1 p1 1* / a 1 ea 1 78 64 p1 0 p1 0 a 0 p1 0* / a 0 ea 0 79 65 p3 0 ddb 0 d 0 d 0 eo 0 80 66 p3 1 ddb 1 d 1 d 1 eo 1 81 67 p3 2 ddb 2 d 2 d 2 eo 2 82 68 p3 3 ddb 3 d 3 d 3 eo 3 83 69 p3 4 ddb 4 d 4 d 4 eo 4 84 70 p3 5 ddb 5 d 5 d 5 eo 5 11 (2) pin functions: table 1-3 gives a concise description of the function of each pin. table 1-3. pin functions (1) type symbol i/o name and function power v cc i power: connected to the power supply (+5v). connect both v cc pins to the system power supply (+5v). v ss i ground: connected to ground (0v). connect all v ss pins to the system power supply (0v). clock xtal i crystal: connected to a crystal oscillator. the crystal frequency should be double the desired system clock frequency. if an external clock is input at the extal pin, a reverse-phase clock should be input at the xtal pin. extal i external crystal: connected to a crystal oscillator or external clock. the frequency of the external clock should be double the desired system clock frequency. see section 16.2, ?scillator circuit?for examples of connections to a crystal and external clock. o system clock: supplies the system clock to peripheral devices. e o enable clock: supplies an e clock to e clock based peripheral devices. system res i reset: a low input causes the h8/330 chip to reset. control stby i standby: a transition to the hardware standby mode (a power-down state) occurs when a low input is received at the stby pin. address a 15 to a 0 o address bus: address output pins. bus 12 table 1-3. pin functions (2) type symbol i/o name and function data bus d 7 to d 0 i/o data bus: 8-bit bidirectional data bus. bus wait i wait: requests the cpu to insert t w states into the bus cycle control when an off-chip address is accessed. rd o read: goes low to indicate that the cpu is reading an external address. wr o write: goes low to indicate that the cpu is writing to an external address. as o address strobe: goes low to indicate that there is a valid address on the address bus. ios o i/o select: goes low when the cpu accesses addresses h?f00 to h?fff. can be used as a chip select signal replacing the upper 8 bits of the address bus when external devices are mapped onto addresses h?f80 to h?f8f and h?fa8 to h?faf. interrupt nmi i nonmaskable interrupt: highest-priority interrupt request. signals the nmieg bit in the system control register determines whether the interrupt is requested on the rising or falling edge of the nmi input. irq 0 to i interrupt request 0 to 7: maskable interrupt request pins. irq 7 operating md 1 , i mode: input pins for setting the mcu operating mode mode md 0 according to the table below. control md 1 md 0 mode description 0 1 mode 1 expanded mode with on-chip rom disabled 1 0 mode 2 expanded mode with on-chip rom enabled 1 1 mode 3 single-chip mode the inputs at these pins are latched in mode select bits 1 to 0 (mds1 and mds0) of the mode register (mdcr) on the rising edge of the res signal. 13 table 1-3. pin functions (3) type symbol i/o name and function serial com- atxd o asynchronous transmit data: asynchronous data output munication pin for the serial communication interface. interface arxd i asynchronous receive data: asynchronous data input pin for the serial communication interface. asck i/o asynchronous serial clock: input/output pin for the asynchronous serial clock. ctxd o clock-synchronized transmit data: synchronous data output pin for the serial communication interface. crxd i clock-synchronized receive data: synchronous data input pin for the serial communication interface. csck i/o clock-synchronized serial clock: input/output pin for the synchronous serial clock. 16-bit free- ftoa, o frt output compare a and b: output pins controlled by running ftob comparators a and b of the free-running timer. timer ftci i frt counter clock input: input pin for an external clock signal for the free-running timer. ftia to i frt input capture a to d: input capture pins for the ftid free-running timer. 8-bit tmo 0 , o 8-bit timer output: compare-match output pins for the timer tmo 1 8-bit timers. tmci 0 , i 8-bit timer counter clock input: external clock input pins tmci 1 for the 8-bit timer counters. tmri 0 , i 8-bit timer counter reset input: a high input at these tmri 1 pins resets the 8-bit timer counters. pwm pw 0 , o pwm timer output (channels 0 and 1): pulse-width timer pw 1 modulation timer output pins. a/d an 7 to an 0 i analog input: analog signal input pins. converter adtrg i a/d trigger: external trigger input for starting the a/d converter. av cc i analog reference voltage: reference voltage pin for the a/d converter. av ss i analog ground: ground pin for the a/d converter. 14 table 1-3. pin functions (4) type symbol i/o name and function dual-port ddb 7 i/o dual-port ram data bus: bidirectional 8-bit bus by which ram to ddb 0 an external cpu can access the dual-port ram. cs i chip select: input pin for selecting the dual-port ram. rs 3 to rs 0 i register select: input pins for addressing the dual-port ram. oe i output enable: enables output on ddb 7 to ddb 0 . we i write enable: enables writing to the dual-port ram. rdy o ready: for sending an interrupt request signal to an external cpu. nmos open-drain output. general- p1 7 to p1 0 i/o port 1: an 8-bit input/output port with programmable mos input purpose pull-ups and led driving capability. the direction of each bit can i/o be selected in the port 1 data direction register (p1ddr). p2 7 to p2 0 i/o port 2: an 8-bit input/output port with programmable mos input pull-ups and led driving capability. the direction of each bit can be selected in the port 2 data direction register (p2ddr). p3 7 to p3 0 i/o port 3: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 3 data direction register (p3ddr). p4 7 to p4 0 i/o port 4: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 4 data direction register (p4ddr). p5 2 to p5 0 i/o port 5: a 3-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 5 data direction register (p5ddr). p6 7 to p6 0 i/o port 6: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 i port 7: an 8-bit input port. p8 6 to p8 0 i/o port 8: a 7-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 8 data direction register (p8ddr). p9 7 to p9 0 i/o port 9: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 9 data direction register (p9ddr). 15 section 2. mcu operating modes and address space 2.1 overview the h8/330 operates in three modes numbered 1, 2, and 3. an additional non-operating mode (mode 0) is used for programming the prom version of the chip. the mode is selected by the inputs at the mode pins (md 1 and md 0 ) at the instant when the chip comes out of a reset. as indicated in table 2-1, the mode determines the size of the address space and the usage of on-chip rom and on-chip ram. the no-rom version (HD6413308) can operate only in mode 1 (expanded mode with on-chip rom disabled). table 2-1. operating modes * in modes 1 and 2, external memory can be accessed instead of on-chip ram by clearing the rame bit in the system control register (syscr) to "0." modes 1 and 2 are referred to as ?xpanded?because they permit access to off-chip memory addresses. md 1 md 0 mode address space on-chip rom on-chip ram low low mode 0 low high mode 1 expanded: 64kb disabled enabled* high low mode 2 expanded: 64kb enabled enabled* high high mode 3 single-chip: about 17kb enabled enabled 17 2.2 mode descriptions mode 1 (expanded mode without on-chip rom): mode 1 supports a 64k-byte address space most of which is off-chip. in particular, the interrupt vector table is located in off-chip memory. the on-chip rom and dual-port ram are not used. software can select whether to use the on-chip ram. ports 1 to 3, 8, and 9 are used for the address and data bus lines and control signals as follows: ports 1 and 2: address bus port 3: data bus port 8 (pin 1), port 9 (pins 7, 5, 4, 3): bus control signals mode 2 (expanded mode with on-chip rom): mode 2 supports a 64k-byte address space of which the first 16k bytes are in on-chip rom. software can select whether or not to use the on- chip ram, and can select the usage of pins in ports 1 and 2. ports 1 and 2: address bus (see note) port 3: data bus port 8 (pin 1), port 9 (pins 7, 5, 4, 3): bus control signals note: in mode 2, ports 1 and 2 are initially general-purpose input ports. software must change the desired pins to output before using them for the address bus. see section 5, ?/o ports?for details. mode 3 (single-chip mode): in this mode all memory is on-chip, in 16k bytes of rom, 512 bytes of ram, and internal i/o registers. if enabled by software, the dual-port ram can be accessed by an external cpu. since no off-chip memory is accessed, there is no address bus; ports 1 and 2 are available for general-purpose input and output. when the dual-port ram is enabled, ports 3, 8, and 9 are used as follows: port 3: dual-port ram data bus port 8 (pins 0 to 3): dual-port ram register select port 9 (pins 7, 5, 4, 3): dual-port ram interface signals the mode in which the dual-port ram is enabled is also called the slave mode. 18 2.3 address space map figure 2-1 shows a memory map in each of the three operating modes. the on-chip register field consists of control, status, and data registers for the on-chip supporting modules, i/o ports, and dual-port ram. off-chip addresses can be accessed only in the expanded modes. access to an off-chip address in the single-chip mode does not cause an address error, but all ??data are returned. 2.3.1 access speed on-chip rom and ram are accessed a word (16 bits) at a time in two states. (a ?tate?is one system clock period.) the on-chip register field is accessed a byte at a time in three states. external memory is accessed a byte at a time in three or more states. the basic bus cycle is three states, but additional wait states can be inserted on request. 2.3.2 ios there are two small gaps in the on-chip address space above the on-chip ram. addresses h?f80 to h?f8f, situated between the on-chip ram and register field, are off-chip. addresses h?fa8 to h?faf are also off-chip. these 24 addresses can be conveniently assigned to external i/o devices. to simplify the addressing of devices at these addresses, an ios signal is provided that goes low when the cpu accesses addresses h?f00 to h?fff. the ios signal can be used in place of the upper 8 bits of the address bus. 19 figure 2-1. address space map * external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to "0". mode 1 (on-chip rom disabled) h'0000 h'003d h'003e h'fd7f vector table external address space on-chip ram, 512 bytes * h'fd80 external address space on-chip rom, 16k bytes mode 2 (on-chip rom enabled) h'0000 h'003d h'003e h'3fff h'fd7f vector table external address space on-chip ram, 512 bytes * h'4000 h'fd80 external address space on-chip rom, 16k bytes mode 3 (single-chip mode) h'0000 h'003d h'003e h'3fff h'ff7f vector table on-chip ram, 512 bytes h'fd80 h'ff90 h'ffa7 h'ffb0 h'ffff on-chip register field external address space external address space on-chip register field on-chip register field on-chip register field on-chip register field on-chip register field h'ff7f h'ff80 h'ff90 h'ffa7 h'ffa8 h'ffaf h'ffb0 h'ffff h'ff8f h'ff7f h'ff80 h'ff90 h'ffa7 h'ffa8 h'ffaf h'ffb0 h'ffff h'ff8f 20 2.4 mode and system control registers (mdcr and syscr) two of the control registers in the register field are the mode control register (mdcr) and system control register (syscr). the mode control register controls the mcu mode: the operating mode of the h8/330 chip. the system control register has bits that enable or disable the on-chip ram and dual-port ram. table 2-2 lists the attributes of these registers. table 2-2. mode and system control registers 2.4.1 mode control register (mdcr) ?h?fc5 bits 7 to 5 and 2?eserved: these bits cannot be modified and are always read as ?. bits 4 and 3?eserved: these bits cannot be modified and are always read as ?. bits 1 and 0?ode select 1 and 0 (mds1 and mds0): these bits indicate the values of the mode pins (md1 and md0) latched on the rising edge of the res signal. these bits can be read but not written. coding example: to test whether the mcu is operating in mode 1: mov.b @h?fc5, r0l cmp.b #h?5, r0l the comparison is with h?5 instead of h?1 because bits 7, 6, 5, and 2 are always read as ?. name abbreviation read/write address mode control register mdcr r h?fc5 system control register syscr r/w h?fc4 bit 7 6 5 4 3 2 1 0 mds1 mds0 initial value 1 1 1 0 0 1 * * read/write r r * initialized according to md1 and md0 inputs. 21 2.4.2 system control register (syscr) ?h?fc4 by setting or clearing the lower two bits of the system control register, software can enable or disable the on-chip ram and dual-port ram. the other bits in the system control register concern the software standby mode and the valid edge of the nmi signal. these bits will be described in section 4, ?xception handling?and section 14, ?ower-down state. bit 1?ual-port ram enable (dpme): in the single-chip mode, this bit enables or disables the dual-port ram. when enabled, the dual-port ram can be accessed by both an external (master) cpu and the on-chip (slave) cpu. when disabled, the dual-port ram can be accessed only by the on-chip cpu. this bit affects the usage of ports 3, 8, and 9. bit 0?am enable (rame): this bit enables or disables the 512-byte on-chip ram. when enabled, the on-chip ram occupies addresses h?d80 to h?f7f of the address space. when the on-chip ram is disabled, accesses to these addresses are directed off-chip. the rame bit is initialized to "1" by a reset, enabling the on-chip ram. the setting of the rame bit is not altered in the sleep mode or software standby mode. it should be cleared to "0" before entering the hardware standby mode. see section 14, "power-down state." bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg dpme rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w bit 1 dpme description 0 the dual-port ram is disabled. (initial state) 1 single-chip mode: the dual-port ram is enabled (slave mode). expanded modes: the dual-port ram is disabled (but can be accessed by the on-chip cpu). bit 0 rame description 0 the on-chip ram is disabled. 1 the on-chip ram is enabled. (initial state) 22 coding examples: to disable the on-chip ram (in expanded modes): bclr #0, @h?fc4 to enable the dual-port ram (in single-chip mode): bset #1, @h?fc4 23 section 3. cpu 3.1 overview the h8/330 chip has the generic h8/300 cpu: an 8-bit central processing unit with a speed- oriented architecture featuring sixteen general registers. this section describes the cpu features and functions, including a concise description of the addressing modes and instruction set. for further details on the instructions, see the h8/300 series programming manual . 3.1.1 features the main features of the h8/300 cpu are listed below. two-way register configuration sixteen 8-bit general registers, or eight 16-bit general registers instruction set with 57 basic instructions, including: multiply and divide instructions powerful bit-manipulation instructions eight addressing modes register direct (rn) register indirect (@rn) register indirect with displacement (@(d:16, rn)) register indirect with post-increment or pre-decrement (@rn+ or @?n) absolute address (@aa:8 or @aa:16) immediate (#xx:8 or #xx:16) pc-relative (@(d:8, pc)) memory indirect (@@aa:8) maximum 64k-byte address space high-speed operation all frequently-used instructions are executed two to four states the maximum clock rate is 10mhz 8- or 16-bit register-register add or subtract: 0.2 s 8 8-bit multiply: 1.4 s 16 8-bit divide: 1.4 s power-down mode sleep instruction 25 3.2 register configuration figure 3-1 shows the register structure of the cpu. there are two groups of registers: the general registers and control registers. figure 3-1. cpu registers 3.2.1 general registers all the general registers can be used as both data registers and address registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). when used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers. r7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. in assembly-language coding, r7 can also be denoted by the letters sp. as indicated in figure 3-2, r7 (sp) points to the top of the stack. 0 7 r0h r0l r1h r1l r2h r2l r3l r3h r4l r4h r5h r5l r6h r6l r7h r7l (sp) 0 15 pc 0 2 3 5 c v z h 0 7 ccr n i 1 7 sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag half-carry flag interrupt mask bit user bit negative flag u u user bit 26 figure 3-2. stack pointer 3.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). (1) program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. each instruction is accessed in 16 bits (1 word), so the least significant bit of the pc is ignored (always regarded as 0). (2) condition code register (ccr): this 8-bit register contains internal status information, including carry (c), overflow (v), zero (z), negative (n), and half-carry (h) flags and the interrupt mask bit (i). bit 7?nterrupt mask bit (i): when this bit is set to ?,?all interrupts except nmi are masked. this bit is set to ??automatically by a reset and at the start of interrupt handling. bit 6?ser bit (u): this bit can be written and read by software for its own purposes. bit 5?alf-carry (h): this bit is set to ??when the add.b, addx.b, sub.b, subx.b, neg.b, or cmp.b instruction causes a carry or borrow out of bit 3, and is cleared to ??otherwise. similarly, it is set to ??when the add.w, sub.w, or cmp.w instruction causes a carry or borrow out of bit 11, and cleared to ??otherwise. it is used implicitly in the daa and das instructions. bit 4?ser bit (u): this bit can be written and read by software for its own purposes. bit 3?egative (n): this bit indicates the most significant bit (sign bit) of the result of an instruction. sp unused area stack area (r7) 27 bit 2?ero (z): this bit is set to ??to indicate a zero result and cleared to ??to indicate a nonzero result. bit 1?verflow (v): this bit is set to ??when an arithmetic overflow occurs, and cleared to ??at other times. bit 0?arry (c): this bit is used by: add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result shift and rotate instructions, to store the value shifted out of the most significant or least significant bit bit manipulation and bit load instructions, as a bit accumulator the ldc, stc, andc, orc, and xorc instructions enable the cpu to load and store the ccr, and to set or clear selected bits by logic operations. some instructions leave some or all of the flag bits unchanged. the action of each instruction on the flag bits is shown in appendix a-1, ?nstruction set list.? see the h8/300 series programming manual for further details. 3.2.3 initial register values when the cpu is reset, the program counter (pc) is loaded from the vector table and the interrupt mask bit (i) in the ccr is set to ?.? the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. to prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 28 3.3 addressing modes the h8/330 supports eight addressing modes. each instruction uses a subset of these addressing modes. (1) register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. in most cases the general register is accessed as an 8-bit register. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. (2) register indirect?rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) register indirect with displacement?(d:16, rn): this mode, which is used only in mov instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. for the mov.w instruction, the resulting address must be even. (4) register indirect with post-increment or pre-decrement?rn+ or @?n: register indirect with post-increment?rn+ the @rn+ mode is used with mov instructions that load registers from memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. the size of the increment is 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. register indirect with pre-decrement??n the @?n mode is used with mov instructions that store register contents to memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. the size of the decrement is 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. (5) absolute address?aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the mov.b instruction uses an 8-bit absolute address of the form h?fxx. the upper 8 bits are assumed to be 1, so the possible address range is h?f00 to h?fff (65280 to 65535). the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. 29 (6) immediate?xx:8 or #xx:16: the instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) pc-relative?(d:8, pc): this mode is used to generate branch addresses in the bcc and bsr instructions. an 8-bit value in byte 2 of the instruction code is added as a sign-extended value to the program counter contents. the result must be an even number. the possible branching range is ?26 to +128 bytes (?3 to +64 words) from the current address. (8) memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address from h?000 to h?0ff (0 to 255). the word located at this address contains the branch address. note that addresses h?000 to h?03d (0 to 61) are located in the vector table. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as ?,?causing word access to be performed at the address preceding the specified address. see section 3.4.2, ?emory data formats?for further information. 30 3.4 data formats the h8/300 cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. all arithmetic and logic instructions except adds and subs can operate on byte data. the daa and das instruction perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. 31 3.4.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 3-3. figure 3-3. register data formats note: rnh: upper digit of general register rnl: lower digit of general register msb: most significant bit lsb: least significant bit 4-bit bcd data 1-bit data 1-bit data byte data byte data word data 4-bit bcd data data type rnl rnh rnl rnh rnl rn rnh register no. don't-care 4 3 7 0 data format 7 0 7 6 5 4 3 2 1 0 don't-care don't-care 7 6 5 4 3 2 1 0 don't-care 7 0 don't-care 7 0 0 15 don't-care 4 3 7 0 7 0 m s b l s b m s b l s b upper digit lower digit upper digit lower digit m s b l s b 32 3.4.2 memory data formats figure 3-4 indicates the data formats in memory. word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as ?.? if an odd address is specified, no address error occurs but the access is performed at the preceding even address. this rule affects mov.w instructions and branching instructions, and implies that only even addresses should be stored in the vector table. figure 3-4. memory data formats the stack must always be accessed a word at a time. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are returned, the lower byte is ignored. 7 0 7 6 5 4 3 2 1 0 1-bit data byte data word data byte data (ccr) on stack word data on stack data type data format address address n address n even address odd address even address odd address even address odd address m s b l s b m s b l s b upper 8 bits lower 8 bits m s b m s b l s b l s b ccr ccr * m s b l s b ccr: condition code register * : ignored when return 33 3.5 instruction set table 3-1 lists the h8/330 instruction set. table 3-1. instruction classification *1 push rn is equivalent to mov.w rn, @?p. pop rn is equivalent to mov.w @sp+, rn. *2 bcc is a conditional branch instruction in which cc represents a condition code. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. function instructions types data transfer mov, movtpe, movfpe, push *1 , pop *1 3 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, 14 daa, das, mulxu, divxu, cmp, neg logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, 8 rotxr bit manipulation bset, bclr, bnot, btst, band, biand, bor, 14 bior, bxor, bixor, bld, bild, bst, bist branch bcc *2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total 57 34 operation notation rd general register (destination) rs general register (source) rn, rm general register r n , r m general register field 3.5.1 data transfer instructions table 3-2 describes the data transfer instructions. figure 3-5 shows their object code formats. table 3-2. data transfer instructions * size: operand size b: byte w: word instruction size* function mov b/w (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:8 or #xx:16, @?n, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @?7 and @r7+ modes require word operands. do not specify byte size for these two modes. movtpe b rs ? (ead) transfers data from a general register to memory in synchronization with the e clock. movfpe b (eas) ? rd transfers data from memory to a general register in synchronization with the e clock. push w rn ? @?p pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @?p. pop w @sp+ ? rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. 36 figure 3-5. data transfer instruction codes 15 8 7 0 mov r r rm ? rn rn ? @rm, or @rm ? rn @(d:16, rm) ? rn, or disp. rn ? @(d:16, rm) @rm+ ? rn, or rn ? @erm abs. @aa:8 ? rn, or rn ? @aa:8 @aa:16 ? rn, or abs. rn ? @aa:16 r #imm. #xx:8 ? rn #xx:16 ? rn #imm. r movfpe, movtpe movfpe: d = 0 movtpe: d = 1 abs. m n r r m n r n n r n n op op op op op op op op r n op push, pop r r m n r r m n r n op notation op: operation field d: direction field (0?oad from; 1?tore to) r m , r n : register field disp.: displacement abs.: absolute address #imm.: immediate data 37 3.5.2 arithmetic operations table 3-3 describes the arithmetic instructions. see figure 3-6 in section 3.5.4, ?hift operations for their object codes. table 3-3. arithmetic instructions * size: operand size b: byte w: word instruction size* function add b/w rd rs ? rd, rd + #imm ? rd sub performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx b rd rs c ? rd, rd #imm c ? rd subx performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc b rd #1 ? rd dec increments or decrements a general register. adds w rd #imm ? rd subs adds or subtracts immediate data to or from data in a general register. the immediate data must be 1 or 2. daa b rd decimal adjust ? rd das decimal-adjusts (adjusts to packed bcd) an addition or subtraction result in a general register by referring to the ccr. mulxu b rd rs ? rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. divxu b rd rs ? rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. cmp b/w rd ?rs, rd ?#imm compares data in a general register with data in another general register or with immediate data. word data can be compared only between two general registers. neg b 0 ?rd ? rd obtains the two s complement (arithmetic complement) of data in a general register. 38 3.5.3 logic operations table 3-4 describes the four instructions that perform logic operations. see figure 3-6 in section 3.5.4, ?hift operations?for their object codes. table 3-4. logic operation instructions 3.5.4 shift operations table 3-5 describes the eight shift instructions. figure 3-6 shows the object code formats of the arithmetic, logic, and shift instructions. table 3-5. shift instructions * size: operand size b: byte instruction size* function and b rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b (rd) ? (rd) obtains the one s complement (logical complement) of general register contents. instruction size* function shal b rd shift ? rd shar performs an arithmetic shift operation on general register contents. shll b rd shift ? rd shlr performs a logical shift operation on general register contents. rotl b rd rotate ? rd rotr rotates general register contents. rotxl b rd rotate through carry ? rd rotxr rotates general register contents through the c (carry) bit. 39 figure 3-6. arithmetic, logic, and shift instruction codes 15 8 7 0 add, sub, cmp addx, subx, mulxu, divxu op adds, subs, inc, dec, daa, das, neg, not op #imm. add, addx, subx, cmp (#xx:8) and, or, xor (rm) #imm. and, or, xor (#xx:8) shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op op op op r m r n r n r n r m r n r n r n notation op: operation field r m , r n : register field #imm.: immediate data 40 3.5.5 bit manipulations table 3-6 describes the bit-manipulation instructions. figure 3-7 shows their object code formats. table 3-6. bit-manipulation instructions (1) * size: operand size b: byte instruction size* function bset b 1 ? ( table 3-6. bit-manipulation instructions (2) * size: operand size b: byte notes on bit manipulation instructions: bset, bclr, bnot, bst, and bist are read-modify- write instructions. they read a byte of data, modify one bit in the byte, then write the byte back. care is required when these instructions are applied to registers with write-only bits and to the i/o port registers. example 1: bclr is executed to clear bit 0 in the port 4 data direction register (p4ddr) under the following conditions. p4 7 : input pin, low, mos pull-up transistor on p4 6 : input pin, high, mos pull-up transistor off p4 5 ?p4 0 : output pins, low the intended purpose of this bclr instruction is to switch p4 0 from output to input. instruction size* function bixor b c ? [( before execution of bclr instruction execution of bclr instruction bclr.b #0, @p4ddr ;clear bit 0 in data direction register after execution of bclr instruction explanation: to execute the bclr instruction, the cpu begins by reading p4ddr. since p4ddr is a write-only register, it is read as h'ff, even though its true value is h'3f. next the cpu clears bit 0 of the read data, changing the value to h'fe. finally, the cpu writes this value (h'fe) back to p4ddr to complete the bclr instruction. as a result, p4 0 ddr is cleared to "0," making p4 0 an input pin. in addition, p4 7 ddr and p4 6 ddr are set to "1," making p4 7 and p4 6 output pins. example 2: bset is executed to set bit 0 in the port 4 data register (p4dr) under the following conditions. p4 7 : input pin, low, mos pull-up transistor on p4 6 : input pin, high, mos pull-up transistor off p4 5 ?p4 0 : output pins, low the intended purpose of this bset instruction is to switch the output level at p4 0 from low to high. p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low low ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 0 pull-up mos on off off off off off off off p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output output output output output output output output input pin state low high low low low low low high ddr 1 1 1 1 1 1 1 0 dr 1 0 0 0 0 0 0 0 pull-up mos off off off off off off off off 43 before execution of bset instruction execution of bset instruction bset.b #0, @port4 ;set bit 0 in data register after execution of bset instruction explanation: to execute the bset instruction, the cpu begins by reading port 4. since p4 7 and p4 6 are input pins, the cpu reads the level of these pins directly, not the value in the data register. it reads p4 7 as low ("0") and p4 6 as high ("1"). since p4 5 to p4 0 are output pins, for these pins the cpu reads the value in the data register ("0"). the cpu therefore reads the value of port 4 as h'40, although the actual value in p4dr is h'80. next the cpu sets bit 0 of the read data to "1," changing the value to h'41. finally, the cpu writes this value (h'41) back to p4dr to complete the bset instruction. as a result, bit p4 0 is set to "1," switching pin p4 0 to high output. in addition, bits p4 7 and p4 6 are both modified, changing the on/off settings of the mos pull-up transistors of pins p4 7 and p4 6 . programming solution: the switching of the pull-ups for p4 7 and p4 6 in example 2 can be avoided by reserving a byte in ram as a temporary register for p4dr and using it as follows. ram0 is a symbol for the user-selected address of the temporary register. p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low low ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 0 pull-up mos on off off off off off off off p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low high ddr 0 0 1 1 1 1 1 1 dr 0 1 0 0 0 0 0 1 pull-up off on off off off off off off 44 before execution of bset instruction mov.b #80, r0l ;write data (h'80) for data register mov.b r0l, @ram0 ;write to dr temporary register (ram0) mov.b r0l, @port4 ;write to dr execution of bset instruction bset.b #0, @ram0 ;set bit 0 in dr temporary register (ram0) after execution of bset instruction mov.b @ram0, r0l ;obtain value of temporary register ram0 mov.b r0l, @port4 ;write value to dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low low ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 0 pull-up mos on off off off off off off off ram0 1 0 0 0 0 0 0 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low high ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 1 pull-up mos on off off off off off off off ram0 1 0 0 0 0 0 0 1 45 figure 3-7. bit manipulation instruction codes 15 8 7 0 bset, bclr, bnot, btst #imm. operand: register direct (rn) bit no.: immediate (#xx:3) r n op r 0 0 0 0 operand: register indirect (@rn) #imm. 0 0 0 0 bit no.: immediate (#xx:3) n op op r 0 0 0 0 operand: register indirect (@rn) r 0 0 0 0 bit no.: register direct (rm) m n op op abs. operand: absolute (@aa:8) #imm. 0 0 0 0 bit no.: immediate (#xx:3) op op r 0 0 0 0 operand: register indirect (@rn) #imm. 0 0 0 0 bit no.: immediate (#xx:3) n op op abs. operand: absolute (@aa:8) #imm. 0 0 0 0 bit no.: immediate (#xx:3) op op r 0 0 0 0 operand: register indirect (@rn) #imm. 0 0 0 0 bit no.: immediate (#xx:3) n op op band, bor, bxor, bld, bst #imm. operand: register direct (rn) bit no.: immediate (#xx:3) r n op biand, bior, bixor, bild, bist #imm. operand: register direct (rn) bit no.: immediate (#xx:3) r n op abs. operand: absolute (@aa:8) 0 0 0 0 bit no.: immediate (#xx:3) #imm. op op operand: register direct (rn) bit no.: register direct (rm) op r n r m abs. operand: absolute (@aa:8) 0 0 0 0 bit no.: register direct (rm) op op r m notation op: operation field r m , r n : register field abs.: absolute address #imm.: immediate data 46 3.5.6 branching instructions table 3-7 describes the branching instructions. figure 3-8 shows their object code formats. table 3-7. branching instructions instruction size function bcc branches if condition cc is true. mnemonic cc field description condition bra (bt) 0 0 0 0 always (true) always brn (bf) 0 0 0 1 never (false) never bhi 0 0 1 0 high c z = 0 bls 0 0 1 1 low or same c z = 1 bcc (bhs) 0 1 0 0 carry clear c = 0 (high or same) bcs (blo) 0 1 0 1 carry set (low) c = 1 bne 0 1 1 0 not equal z = 0 beq 0 1 1 1 equal z = 1 bvc 1 0 0 0 overflow clear v = 0 bvs 1 0 0 1 overflow set v = 1 bpl 1 0 1 0 plus n = 0 bmi 1 0 1 1 minus n = 1 bge 1 1 0 0 greater or equal n ? v = 0 blt 1 1 0 1 less than n ? v = 1 bgt 1 1 1 0 greater than z (n ? v) = 0 ble 1 1 1 1 less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address. jsr branches to a subroutine at a specified address. bsr branches to a subroutine at a specified displacement from the current address. rts returns from a subroutine 47 figure 3-8. branching instruction codes 15 8 7 0 cc disp. bcc 0 0 0 0 jmp (@rm) jmp (@aa:16) abs. abs. jmp (@@aa:8) disp. bsr r 0 0 0 0 jsr (@rm) jsr (@aa:16) abs. jsr (@@aa:8) rts m r m op op op op op op op op abs. op notation op: operation field cc: condition field r m : register field disp.: displacement abs.: absolute address 48 3.5.7 system control instructions table 3-8 describes the system control instructions. figure 3-9 shows their object code formats. table 3-8. system control instructions instruction size function rte returns from an exception-handling routine. sleep causes a transition to the power-down state. ldc b rs ? ccr, #imm ? ccr moves immediate data or general register contents to the condition code register. stc b ccr ? rd copies the condition code register to a specified general register. andc b ccr #imm ? ccr logically ands the condition code register with immediate data. orc b ccr #imm ? ccr logically ors the condition code register with immediate data. xorc b ccr ? #imm ? ccr logically exclusive-ors the condition code register with immediate data. nop pc + 2 ? pc only increments the program counter. * size: operand size b: byte 49 figure 3-9. system control instruction codes 3.5.8 block data transfer instruction in the h8/330 the eepmov instruction is a block data transfer instruction. it does not have the eeprom write function it has in some other chips. table 3-9 describes the eepmov instruction. figure 3-10 shows its object code format. table 3-9. block data transfer instruction/eeprom write operation 15 8 7 0 rte, sleep, nop op r ldc, stc (rn) #imm. andc, orc, xorc, ldc (#xx:8) n op op notation op: operation field r n : register field #imm.: immediate data instruction size function eepmov if r4l 0 then repeat @r5+ ? @r6+ r4l ?1 ? r4l until r4l = 0 else next; moves a data block according to parameters set in general registers r4l, r5, and r6. r4l: size of block (bytes) r5: starting source address r6: starting destination address execution of the next instruction starts as soon as the block transfer is completed. 50 figure 3-10. block data transfer instruction/eeprom write operation code notes on eepmov instruction 1. the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. 2. when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. 3.6 cpu states the cpu has three states: the program execution state, exception-handling state, and power-down state. the power-down state is further divided into three modes: the sleep mode, software standby mode, and hardware standby mode. figure 3-11 summarizes these states, and figure 3-12 shows a map of the state transitions. figure 3-11. operating states 15 8 7 0 op op eeprom state program execution state the cpu executes successive program instructions. exception-handling state a transient state triggered by a reset or interrupt. the cpu executes a hardware sequence that includes loading the program counter from the vector table. power-down state sleep mode a state in which some or all of the chip software standby mode functions are stopped to conserve power. hardware standby mode r5 ? r5 + r4l ? ? r6 ? r6 + r4l h'ffff not allowed r5 ? r5 + r4l ? ? r6 ? r6 + r4l 51 notation o p : operation field figure 3-12. state transitions 3.6.1 program execution state in this state the cpu executes program instructions in sequence. the main program, subroutines, and interrupt-handling routines are all executed in this state. 3.6.2 exception-handling state the exception-handling state is a transient state that occurs when the cpu is reset or accepts an interrupt. in this state the cpu carries out a hardware-controlled sequence that prepares it to execute a user-coded exception-handling routine. in the hardware exception-handling sequence the cpu does the following: (1) saves the program counter and condition code register to the stack (except in the case of a reset). (2) sets the interrupt mask (i) bit in the condition code register to ?. (3) fetches the start address of the exception-handling routine from the vector table. (4) branches to that address, returning to the program execution state. see section 4, ?xception handling,?for further information on the exception-handling state. reset state hardware standby mode interrupt request res = 1 power-down state sleep mode exception - handling state program execution state exception- handing request exception handing sleep instruction with ssby bit set stby=1 or res=0 sleep instruction software standby mode notes: 1. a transition to the reset state occurs when res goes low, except when the chip is in the hardware standby mode. 2. a transition from any state to the hardware standby mode occurs when stby goes low. nmi or irq 0 to irq 7 exception handling request 52 3.6.3 power-down state the power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) sleep mode: the sleep mode is entered when a sleep instruction is executed. the cpu halts, but cpu register contents remain unchanged and the on-chip supporting modules continue to function. when an interrupt or reset signal is received, the cpu returns through the exception-handling state to the program execution state. (2) software standby mode: the software standby mode is entered if the sleep instruction is executed while the ssby (software standby) bit in the system control register (syscr) is set. the cpu and all on-chip supporting modules halt. the on-chip supporting modules are initialized, but the contents of the on-chip ram and cpu registers remain unchanged. i/o port outputs also remain unchanged. (3) hardware standby mode: the hardware standby mode is entered when the input at the stby pin goes low. all chip functions halt, including i/o port output. the on-chip supporting modules are initialized, but on-chip ram contents are held. see section 14, ?ower-down state?for further information. 3.7 access timing and bus cycle the cpu is driven by the system clock ( ). the period from one rising edge of the system clock to the next is referred to as a ?tate. memory access is performed in a two-or three-state bus cycle as described below. for more detailed timing diagrams of the bus cycles, see section 17, ?lectrical specifications. 3.7.1 access to on-chip memory (ram and rom) on-chip rom and ram are accessed in a cycle of two states designated t 1 and t 2 . either byte or word data can be accessed, via a 16-bit data bus. figure 3-13 shows the on-chip memory access cycle. figure 3-14 shows the associated pin states. 53 figure 3-13. on-chip memory access cycle figure 3-14. pin states during on-chip memory access cycle bus cycle t1 state t2 state internal address bus address write data internal read signal internal data bus (read) read data internal write signal internal data bus (write) t2 state bus cycle t1 state address bus address data bus: high impedance state as: high rd: high wr: high 54 3.7.2 access to on-chip register field and external devices the on-chip register field (i/o ports, dual-port ram, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: t 1 , t 2 , and t 3 . only one byte of data can be accessed per cycle, via an 8-bit data bus. access to word data or instruction codes requires two consecutive cycles (six states). wait states: if requested, additional wait states (t w ) are inserted between t 2 and t 3 . the wait pin is sampled at the center of state t 2 . if it is low, a wait state is inserted after t 2 . the wait pin is also sampled at the center of each wait state and if it is still low, another wait state is inserted. an external device can have any number of wait states inserted by holding wait low for the necessary duration. the bus cycle for the movtpe and movfpe instructions will be described in section 15, "e-clock interface." figure 3-15 shows the access cycle for the on-chip register field. figure 3-16 shows the associated pin states. figures 3-17 (a) and (b) show the read and write access timing for external devices. figure 3-15. on-chip register field access cycle write data bus cycle t1 state t2 state t3 state internal address bus address internal read signal internal data bus (read) read data internal write signal internal data bus (write) 55 figure 3-16. pin states during on-chip register field access cycle figure 3-17 (a). external device access timing (read) bus cycle t1 state t2 state t3 state address bus address as: high rd: high wr: high data bus: high impedance state read cycle t1 state t2 state t3 state address bus address read data as rd wr: high data bus 56 figure 3-17 (b). external device access timing (write) write cycle t1 state t2 state t3 state address bus address write data as rd: high wr data bus 57 section 4. exception handling as indicated in table 4-1, the h8/330 recognizes only two kinds of exceptions: interrupts (28 sources) and the reset. there are no error or trap exceptions. when an exception occurs the cpu enters the exception-handling state and performs a hardware exception-handling sequence. there are two exception-handling sequences: one for the reset and one for interrupts. in both sequences the cpu: sets the interrupt mask (i) bit in the ccr to ?,?and loads the program counter (pc) from the vector table. after the program counter is loaded, the cpu returns to the program execution state and program execution starts from the new pc address. the vector table occupies addresses h?000 to h?03d in memory. it consists of word entries giving the addresses of software interrupt-handling routines and the reset routine. the entries are indexed by a vector number associated with the particular exception. for an interrupt, before the pc and ccr are altered as described above, the old pc and ccr contents are pushed on the stack, so that they can be restored when an rte (return from exception ) instruction is executed. if a reset and interrupt occur simultaneously, the reset has priority. there is also a priority order among different types of interrupts. table 4-1 compares the reset and interrupt exceptions. table 4-1. reset and interrupt exceptions item reset interrupt priority highest lower cause low res input internal or external interrupt signal when detected any clock period at end of current instruction, unless current instruction is andc, orc, xorc, or ldc, or at end of hardware interrupt-handling sequence. when handled immediately at end of current instruction. vector numbers 0 3 to 30 vector table h?000 ?h?001 h?006 ?h?03d 59 4.1 reset a reset has the highest exception-handling priority. when the res pin goes low, all current processing by the cpu and on-chip supporting modules halts. when res returns from low to high, the following hardware reset sequence is executed. (1) the value at the mode pins (md 1 and md 0 ) is latched in bits mds1 and mds0 of the mode register (mdcr). (2) in the condition code register (ccr), the i bit is set to ??to mask interrupts. (3) the registers of the i/o ports and on-chip supporting modules are initialized. (4) the cpu loads the program counter with the first word in the vector table (stored at addresses h?000 and h?001) and starts program execution. a reset does not initialize the general registers or on-chip ram. all interrupts, including nmi, are disabled immediately after a reset. the first program instruction, located at the address specified at the top of the vector table, is therefore always executed. this instruction should be a mov.w instruction initializing the stack pointer (r7). after execution of this instruction, the nmi interrupt is enabled. other interrupts remain disabled until their enable bits are set to ??and the interrupt mask is cleared. to ensure correct resetting, at power-on the res pin should be held low for at least 20ms. in a reset during operation, the res pin should be held low for at least 10 system clock periods. the res pin should also be held low when power is switched off. figure 4-1 indicates the timing of the reset sequence when the vector table and reset routine are located in on-chip rom. figure 4-2 indicates the timing when they are in off-chip memory. 60 figure 4-1. reset sequence (mode 2 or 3, reset routine in on-chip rom) (1) (2) (3) res (2) internal address bus internal read signal internal write signal internal data bus (16 bits) (1) reset vector address (h'0000) (2) starting address of reset routine (contents of h'0000?'0001) (3) first instruction of reset routine vector fetch internal processing instruction prefetch 61 (1) (2) (3) (4) (5) (6) (7) (8) (1),(3) reset vector address: (1)=h'0000, (3)=h'0001 (2),(4) starting address of reset routine (contents of reset vector): (2)=upper byte, (4)=lower byte (5),(7) starting address of reset routine: (5)=(2)(4), (7)=(2)(4)+1 (6),(8) first instruction of reset routine: (6)=first byte, (8)=second byte vector fetch internal process- ing instruction prefetch res d 7 to d 0 (8 bits) a 15 to a 0 rd wr figure 4-2. r eset sequence (mode 1) 62 4.2 interrupts there are nine input pins for external interrupts (nmi, irq 0 to irq 7 ). there are also 19 internal interrupts originating in the 16-bit free-running timer (frt), 8-bit timers (tmr0 and tmr1), serial communication interface (sci), and a/d converter. the features of these interrupts are: all internal and external interrupts except nmi can be masked by the i bit in the ccr. irq 0 to irq 7 can be edge-sensed or level-sensed. (the falling edge or low level is active.) the type of sensing can be selected for each interrupt individually. nmi is edge-sensed, and either the rising or falling edge can be selected. interrupts are individually vectored. the software interrupt-handling routine does not have to determine what type of interrupt has occurred. table 4-2 lists all the interrupts in their order of priority and gives their vector numbers and the addresses of their entries in the vector table. 63 table 4-2. interrupts notes: 1. h?000 and h'0001 contain the reset vector. 2. h?002 to h?005 are reserved by the h8/330 and are not available to the user. vector address priority source interrupt no. of vector high external nmi 3 h?006 interrupts irq 0 4 h?008 irq 1 5 h?00a irq 2 6 h?00c irq 3 7 h?00e irq 4 8 h?010 irq 5 9 h?012 irq 6 10 h?014 irq 7 11 h?016 free-running icia (input capture a) 12 h?018 timer icib (input capture b) 13 h?01a icic (input capture c) 14 h?01c icid (input capture d) 15 h?01e ocia (output compare a) 16 h?020 ocib (output compare b) 17 h?022 fovi (overflow) 18 h?024 8-bit timer 0 cmi0a (compare-match a) 19 h?026 cmi0b (compare-match b) 20 h?028 ovi0 (overflow) 21 h?02a 8-bit timer 1 cmi1a (compare-match a) 22 h?02c cmi1b (compare-match b) 23 h?02e ovi1 (overflow) 24 h?030 dual-port mrei (master read end) 25 h?032 ram mwei (master write end) 26 h?034 serial eri (receive error) 27 h?036 communication rxi (receive end) 28 h?038 interface txi (transmit end) 29 h?03a low a/d converter adi (conversion end) 30 h?03c 64 figure 4-3 shows a block diagram of the interrupt controller. figure 4-4 is a flowchart showing the operation of the interrupt controller and the sequence by which an interrupt is accepted. this sequence is outlined below. (1) the interrupt controller receives an interrupt request signal. interrupt request signals can be generated by: a high-to-low (or low-to-high) transition of the nmi signal a low input (or high-to-low transition) of one of the irq 0 to irq 7 signals an on-chip supporting module all interrupts except nmi have enable bits. the interrupt can be requested only when its enable bit is set to "1." (2) when notified of an interrupt, the interrupt controller scans the interrupt signals in priority order and selects the one with the highest priority. (see table 4-2 for the priority order.) other requested interrupts remain pending. (3) the interrupt controller accepts the interrupt if it is an nmi, or if it is another interrupt and the i bit in the ccr is cleared to ?.? if the interrupt is not an nmi and the i bit is set to ?,?the interrupt is held pending. (4) when an interrupt is accepted, after completion of the current instruction, the cpu pushes first the pc then the ccr onto the stack. the stacked pc indicates the address of the first instruction that will be executed after the return. the stack pointer (r7) must indicate an even address. see section 4.2.5, ?ote on stack handling?for details. (5) the cpu sets the i bit in the ccr to ?,?masking all further interrupts except nmi during the interrupt-handling routine. (6) the cpu generates the vector address of the interrupt and loads the word at this address into the program counter. (7) execution of the software interrupt-handling routine starts from the address now in the pro- gram counter. (8) on the return from the interrupt-handling routine (rte instruction), the ccr and pc are popped from the stack and execution of the interrupted program resumes. the timing of this sequence is shown in figure 4-5 for the case in which the program and vector table are in on-chip rom and the stack is in on-chip ram. 65 figure 4-3. block diagram of interrupt controller external (irq 0 to irq 7 ) or internal interrupt enable signal external (irq 0 to irq 7 ) or internal interrupt nmi request priority decision logic interrupt request interrupt controller ccr in cpu i nmi 66 figure 4-4. hardware interrupt-handling sequence program execution interrupt request present? adi? i=0 in ccr? pending save pc save ccr i 1, masking all interrupts except nmi nmi? y n y y y y y n n irq 0 ? n n ? pc: program counter ccr: condition code register i: interrupt mask bit irq 1 ? to software interrupt-handling routine 67 figure 4-5. timing of interrupt sequence (3) (5) (6) (8) (9) (1) interrupt priority decision. wait for end of instruction. interrupt accepted internal process- ing stack vector table fetch internal process- ing instruction fetch (first instruction of interrupt-handling routine) interrupt request signal internal address bus internal write signal internal read signal internal 16-bit data bus (1) instruction prefetch address (pushed on stack. instruction is executed on return from interrupt-handling routine.) (2) (4) instruction code (not executed) (3) instruction prefetch address (not executed) (5) sp? (6) sp? (7) ccr (8) address of vector table entry (9) vector table entry (address of first instruction interrupt-handling routine) (10) first instruction of interrupt-handling routine (1) (2) (4) (7) (9) (10) instruction fetch (1) instruction prefetch address (pushed on stack. instruction is executed on return from interrupt-handling routine.) (2) (4) instruction code (not executed) (3) instruction prefetch address (not executed) (5) sp? (6) sp? (7) ccr (8) address of vector table entry (9) vector table entry (address of first instruction interrupt-handling routine) (10) first instruction of interrupt-handling routine 68 4.2.1 interrupt-related registers the interrupt controller refers to three registers in addition to the ccr. the names and attributes of these registers are listed in table 4-3. table 4-3. registers read by interrupt controller (1) system control register (syscr)??fc4 the first four bits of the system control register concern the software standby mode, and the last two bits enable the on-chip ram and dual-port ram. bit 2 is the only bit read by the interrupt controller. bit 2?onmaskable interrupt edge (nmieg): this bit determines whether a nonmaskable interrupt is generated on the falling or rising edge of the nmi input signal. (2) irq sense control register (iscr)??fc6 name abbreviation read/write address system control register syscr r/w h?fc4 irq sense control register iscr r/w h?fc6 irq enable register ier r/w h?fc7 bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg dpme rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w bit 2 nmieg description 0 an interrupt is generated on the falling edge of nmi. (initial state) 1 an interrupt is generated on the rising edge of nmi. bit 7 6 5 4 3 2 1 0 irq 7 sc irq 6 sc irq 5 sc irq 4 sc irq 3 sc irq 2 sc irq 1 sc irq 0 sc initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 69 bits 0 to 7 ?irq 0 to irq 7 sense control (irq 0 sc to irq 7 sc): these bits determine whether the irq 0 to irq 7 inputs are edge-sensed or level-sensed. edge-sensed interrupt signals are latched (if enabled) until the interrupt is serviced. they are latched even if the interrupt mask bit (i) is set in the ccr, and remain latched even if the enable bit (irq 0 e to irq 7 e) is later cleared to 0. (3) irq enable register (ier)??fc7 bits 0 to 7 ?irq 0 to irq 7 enable (irq 0 e to irq 7 e): these bits enable or disable the irqi signals individually. after a reset, all irqi interrupts are disabled (as well as masked). 4.2.2 external interrupts the external interrupts are nmi and irq 0 to irq 7 . (1) nmi: a nonmaskable interrupt is generated on the rising or falling edge of the nmi input signal regardless of whether the i (interrupt mask) bit is set in the ccr. the valid edge is selected by the nmieg bit in the system control register. an nmi has highest priority and is always accepted as soon as the current instruction ends, unless the current instruction is an andc, orc, xorc, or ldc instruction. when an nmi interrupt is bit i irqisc description 0 irqi is level-sensed. (initial state) 1 irqi is sensed on the falling edge. bit 7 6 5 4 3 2 1 0 irq 7 e irq 6 e irq 5 e irq 4 e irq 3 e irq 2 e irq 1 e irq 0 e initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit i irqie description 0 irqi is disabled. (initial state) 1 irqi is enabled. 70 accepted the interrupt mask (i bit) is set, so the nmi handling routine cannot be interrupted except by another nmi. the nmi vector number is 3. its entry is located at address h?006 in the vector table. (2) irq 0 to irq 7 : these interrupt signals are level-sensed or sensed on the falling edge of the input, as selected by the bits in the iscr. these interrupts can be masked collectively by the i bit in the ccr, and can be enabled and disabled individually by setting and clearing the bits in the ier. when one of these interrupts is accepted, the i bit is set to "1" to mask further interrupts (except nmi). the interrupt controller reads level-sensed signals directly from the input pin, so the signal must be held low until the interrupt is accepted. edge-sensed signals are latched in a flip-flop in the interrupt controller. the signal is latched only if the interrupt is enabled in the irq enable register. however, the signal is latched even if the interrupt is masked (i bit set to ??in the ccr). these interrupts are second in priority to nmi. among them, irq 0 has the highest priority and irq 7 the lowest priority. interrupts irq 0 to irq 7 occur regardless of whether the irq 0 to irq 7 lines are used for input or output. when irq 0 to irq 7 are requested by external signals, clear the corresponding bits in the port data direction register (ddr) to 0, and do not use the same pins for timer or serial communication interface input or output. 4.2.3 internal interrupts nineteen internal interrupts can be requested by the on-chip supporting modules. all of them are masked when the i bit in the ccr is set. in addition, they can all be enabled or disabled by bits in the control registers of the on-chip supporting modules. when one of these interrupts is accepted, the i bit is set to "1" to mask further interrupts (except nmi). power can be conserved by waiting for an internal interrupt in the sleep mode, in which the cpu halts but the on-chip supporting modules continue to run. when the interrupt arrives, the cpu returns to the program-execution state, services the interrupt, then resumes execution of the main program. see section 14, ?ower-down state?for further information on the sleep mode. the internal interrupt signals received by the interrupt controller are generated from flag bits in the 71 registers of the on-chip supporting modules. the interrupt controller does not reset these flag bits when accepting the interrupt. the flag bit must be reset by the software interrupt-handling routine. to reset an interrupt flag, software must read the relevant bit or register, then clear the flag bit to ?.? the flag bit cannot be cleared unless it is first read. the following is a coding example that clears the a/d interrupt flag (adf bit) in the a/d control/status register. bclr #7, @h?fe8 note: when disabling internal interrupts, note the following points. 1. set the interrupt mask (i) to "1" before disabling an internal interrupt (an interrupt from an on- chip supporting module) or clearing an interrupt flag. 2. if an instruction that disables an internal interrupt is executed while the interrupt mask (i) is cleared to "0", and the interrupt is requested during execution of the instruction, the cpu resolves this conflict as follows: if one or more other interrupts are also requested, the other interrupt with the highest priority is serviced. if no other interrupt is requested, the cpu branches to the reset address. example: the following coding disables the output compare a interrupt from the free-running timer module in the h8/330 by clearing the ociae bit. the i bit is first set to "1." orc #80, ccr ; set i bit bclr #3, @tier ; disable output compare a interrupt andc #7f, ccr ; clear i bit note: interrupt requests are not detected immediately after the andc, orc, xorc, and ldc instructions. for the priority order of these interrupts, see table 4-2. 4.2.4 interrupt response time table 4-4 indicates the time that elapses from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. since the h8/330 accesses its on-chip memory 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip rom and the stack in on-chip ram. 72 table 4-4. number of states before interrupt service notes: 1. these values do not apply if the current instruction is an eepmov, movfpe, or movtpe instruction. 2. if wait states are inserted in external memory access, these values may be longer. 3. 1 for internal interrupts. 4.2.5 note on stack handling when the h8/330 performs word access, the least significant bit of the address is always assumed to be ?.? if an odd address is specified, no address error occurs, but the intended address is not accessed. the stack is always accessed by word access. care should be taken to keep an even value in the stack pointer (general register r7). the push and pop (or mov.w rn, @?p and mov.w @sp+, rn) instructions should be used for pushing and popping registers on the stack. the mov.b rn, @?p and mov.b @sp+, rn instructions should never be used; they can easily cause programs to crash. figure 4-6 shows how the pc and ccr are pushed on the stack during the hardware interrupt- handling sequence. the ccr is saved as a word consisting of two identical bytes, both containing the ccr value. on return from the interrupt-handling routine, the ccr is popped from the upper of these two bytes. the lower byte is ignored. number of states no. reason for wait on-chip memory external memory 1 interrupt priority decision 2 (note 3) 2 (note 3) 2 wait for completion of 1 to 13 5 to 17 (note 2) current instruction (note 1) 3 save pc and ccr 4 12 (note 2) 4 fetch vector 2 6 (note 2) 5 fetch instruction 4 12 (note 2) 6 internal processing 4 4 total 17 to 29 41 to 53 (note 2) 73 figure 4-7 shows an example of damage caused when the stack pointer contains an odd address. figure 4-6. usage of stack in interrupt handling sp(r7) sp-4 sp-3 sp-2 sp-1 sp(r7) stack area sp+1 sp+2 sp+3 sp+4 even address ccr ccr * pc (upper byte) pc (lower byte) before interrupt is accepted after interrupt is accepted pushed onto stack program counter condition code register stack pointer pc ccr sp : : : 1. 2. the pc contains the address of the first instruction executed after return. registers must be saved and restored by word access at an even address. notes: * ignored on return. : 74 figure 4-7. example of damage caused by setting an odd address in r7 4.2.6 deferring of interrupts as noted previously, no interrupt is accepted immediately after a reset. system control instructions that rewrite the ccr have a similar effect. interrupts requests received during one of these instructions are deferred until at least one more instruction has been executed. the instructions that defer interrupts in this way are xorc, orc, andc, and ldc. at the completion of these instructions the interrupt controller does not check the interrupt signals. the cpu therefore always proceeds to the next instruction. (and if the next instruction is one of these four, the cpu also proceeds to the next instruction after that.) the interrupt-handling sequence starts after the next instruction that is not one of these four has been executed. figure 4-8 shows an example. pc h r1 sp sp sp l pc l pc h'ffcd h'ffcf h'ffcc bsr instruction mov.b r1l, @?7 pc is improperly stored beyond top of stack h'ffcf set in sp pc is lost h pc : upper byte of program counter lower byte of program counter general register stack pointer pc : r1 : sp : h l l l 75 nmi and other edge-sensed interrupt request signals that arrive during the execution of an andc, orc, xorc, or ldc instruction are not lost. the request is latched in the interrupt controller and detected after another instruction has been executed. figure 4-8. example of deferred interrupt program flow ldc.b #h?0 ? interrupt request: ignored by interrupt controller mov.w #h?f80,sp ? cpu executes next instruction: interrupt controller now detects interrupt request push r1 ? to interrupt-handling sequence 76 section 5. i/o ports 5.1 overview the h8/330 has nine parallel i/o ports, including: six 8-bit input/output ports?orts 1, 2, 3, 4, 6, and 9 one 8-bit input port?ort 7 one 7-bit input/output port?ort 8 one 3-bit input/output port?ort 5 all ports except port 7 have programmable mos input pull-ups. ports 1 and 2 can drive leds. input and output are memory-mapped. the cpu views each port as a data register (dr) located in the register field at the high end of the address space. each port (except port 7) also has a data direction register (ddr) which determines which pins are used for input and which for output. output: to send data to an output port, the cpu selects output in the data direction register and writes the desired data in the data register, causing the data to be held in a latch. the latch output drives the pin through a buffer amplifier. if the cpu reads the data register of an output port, it obtains the data held in the latch rather than the actual level of the pin. input: to read data from an i/o port, the cpu selects input in the data direction register and reads the data register. this causes the input logic level at the pin to be placed directly on the internal data bus. there is no intervening input latch. mos pull-up: the mos pull-ups for input pins are controlled as follows. to turn on the pull-up transistor for a pin, software must first clear its data direction bit to ??to make the pin an input pin, then write a ??in the data bit for that pin. the pull-up can be turned off by writing a ??in the data bit, or a ??in the data direction bit. the pull-ups are also turned off by a reset and by entry to the hardware standby mode. the data direction registers are write-only registers; their contents are invisible to the cpu. if the cpu reads a data direction register all bits are read as ?,?regardless of their true values. care is required if bit manipulation instructions are used to set and clear the data direction bits. see the note on bit manipulation instructions in section 3.5.5, "bit manipulations." auxiliary functions: in addition to their general-purpose input/output functions, all of the i/o ports have auxiliary functions. most of the auxiliary functions are software-selectable and must be enabled by setting bits in control registers. when selected, an auxiliary function usually replaces 77 the general-purpose input/output function, but in some cases both functions can operate simultaneously. table 5-1 summarizes the auxiliary functions of the ports. table 5-1. auxiliary functions of input/output ports notes: *1 selected automatically in mode 1; software-selectable in mode 2 *2 selected automatically in modes 1 and 2 5.2 port 1 port 1 is an 8-bit input/output port that also provides the low bits of the address bus. the function of port 1 depends on the mcu mode as indicated in table 5-2. table 5-2. functions of port 1 * depending on the bit settings in the data direction register: 0?nput pin; 1?ddress pin pins of port 1 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive light-emitting diodes and a darlington pair. when they are used as input pins, they have programmable mos pull-ups. mode 1 mode 2 mode 3 address bus (low) input port or input/output port (a 7 to a 0 ) address bus (low) (a 7 to a 0 )* i/o port expanded modes single-chip mode port 1 address bus (low)* 1 port 2 address bus (high)* 1 port 3 data bus* 2 dual-port ram data bus port 4 8-bit and pwm timer input and output port 5 serial communication (asynchronous mode) port 6 free-running timer input/output, irq 6 and irq 7 port 7 analog input port 8 serial communication (synchronous serial communication (synchronous mode) mode) e clock and ios output dual-port ram address select input irq 3 to irq 5 irq 3 to irq 5 port 9 bus control and output* 2 dual-port ram interface control, output irq 0 to irq 2 and adtrg irq 0 to irq 2 and adtrg 78 table 5-3 details the port 1 registers. table 5-3. port 1 registers port 1 data direction register (p1ddr)??fb0 p1ddr is an 8-bit register that selects the direction of each pin in port 1. a pin functions as an output pin if the corresponding bit in p1ddr is set to ?,?and as an input pin if the bit is cleared to ?. port 1 data register (p1dr)??fb2 p1dr is an 8-bit register containing the data for pins p1 7 to p1 0 . when the cpu reads p1dr, for output pins it reads the value in the p1dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p1dr latch. mos pull-ups: are available for input pins in modes 2 and 3. software can turn on the mos pull-up by writing a ??in p1dr, and turn it off by writing a ?.? the pull-ups are automatically turned off for output pins in modes 2 and 3, and for all pins in mode 1. bit 7 6 5 4 3 2 1 0 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w name abbreviation read/write initial value address port 1 data direction register p1ddr w h?f (mode 1) h?fb0 h?0 (modes 2 and 3) port 1 data register p1dr r/w h?0 h?fb2 79 mode 1: in mode 1 (expanded mode without on-chip rom), port 1 is automatically used for address output. the port 1 data direction register is unwritable. all bits in p1ddr are automatically set to "1" and cannot be cleared to "0." mode 2: in mode 2 (expanded mode with on-chip rom), the usage of port 1 can be selected on a pin-by-pin basis. a pin is used for general-purpose input if its data direction bit is cleared to "0," or for address output if its data direction bit is set to ?. mode 3: in the single-chip mode port 1 is a general-purpose input/output port. reset: a reset clears p1ddr and p1dr to all ?,? placing all pins in the input state with the mos pull-ups off. in mode 1, when the chip comes out of reset, p1ddr is set to all "1." hardware standby mode: all pins are placed in the high-impedance state with the mos pull-ups off. software standby mode: in the software standby mode, both p1ddr and p1dr remain in their previous state. address output pins are low. general-purpose output pins continue to output the data in p1dr. figure 5-1 shows a schematic diagram of port 1. 80 figure 5-1. port 1 schematic diagram 5.3 port 2 port 2 is an 8-bit input/output port that also provides the high bits of the address bus. the function of port 2 depends on the mcu mode as indicated in table 5-4. table 5-4. functions of port 2 mode 1 mode 2 mode 3 address bus (high) input port or input/output port (a 15 to a 8 ) address bus (high) (a 15 to a 8 )* * depending on the bit settings in the data direction register: 0?nput pin; 1?ddress pin p1 n r q d c r q d c internal data bus internal address bus hardware standby mode 3 mode 1 or 2 reset wp1 mode 1 reset s* wp1d p1n ddr p1n dr rp1 wp1d: write port 1 ddr wp1: write port 1 rp1: read port 1 n =0 to7 * set-priority * 81 pins of port 2 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive light-emitting diodes and a darlington pair. when they are used as input pins, they have programmable mos pull-ups. table 5-5 details the port 2 registers. table 5-5. port 2 registers name abbreviation read/write initial value address port 2 data direction p2ddr w h?f (mode 1) h?fb1 register h'00 (modes 2 and 3) port 2 data register p2dr r/w h?0 h?fb3 port 2 data direction register (p2ddr)??fb1 p2ddr is an 8-bit register that selects the direction of each pin in port 2. a pin functions as an output pin if the corresponding bit in p2ddr is set to ?,?and as an input pin if the bit is cleared to ?. port 2 data register (p2dr)??fb3 p2dr is an 8-bit register containing the data for pins p2 7 to p2 0 . when the cpu reads p2dr, for output pins it reads the value in the p2dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p2dr latch. bit 7 6 5 4 3 2 1 0 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 82 mos pull-ups: are available for input pins in modes 2 and 3. software can turn on the mos pull-up by writing a ??in p2dr, and turn it off by writing a ?.? the pull-ups are automatically turned off for output pins in modes 2 and 3, and for all pins in mode 1. mode 1: in mode 1 (expanded mode without on-chip rom), port 2 is automatically used for address output. the port 2 data direction register is unwritable. all bits in p2ddr are automatically set to "1" and cannot be cleared to "0." mode 2: in mode 2 (expanded mode with on-chip rom), the usage of port 2 can be selected on a pin-by-pin basis. a pin is used for general-purpose input if its data direction bit is cleared to "0," or for address output if its data direction bit is set to ?. mode 3: in the single-chip mode port 2 is a general-purpose input/output port. reset: a reset clears p2ddr and p2dr to all ?,?placing all pins in the input state with the mos pull-ups off. in mode 1, when the chip comes out of reset, p2ddr is set to all "1." hardware standby mode: all pins are placed in the high-impedance state with the mos pull-ups off. software standby mode: in the software standby mode, both p2ddr and p2dr remain in their previous state. address output pins are low. general-purpose output pins continue to output the data in p2dr. figure 5-2 shows a schematic diagram of port 2. 83 figure 5-2. port 2 schematic diagram 5.4 port 3 port 3 is an 8-bit input/output port that also provides the external data bus and dual-port ram (master-slave) data bus. the function of port 3 depends on the mcu mode as indicated in table 5-6. table 5-6. functions of port 3 mode 3 mode 1 mode 2 dpme = "0" dpme = "1" data bus data bus input/output port dual-port ram data bus pins of port 3 can drive a single ttl load and a 90pf capacitive load when they are used as output internal data bus p2 n r q d c r q d c internal address bus hardware standby mode 3 mode 1, or 2 reset wp2 mode 1 reset s* wp2d p2n ddr p2n dr rp2 wp2d: write port 2 ddr wp2: write port 2 rp2: read port 2 n = 0 to7 * set-priority * mode 1 or 2 84 pins. they can also drive a darlington pair. when they are used as input pins, they have programmable mos pull-ups. table 5-7 details the port 3 registers. table 5-7. port 3 registers name abbreviation read/write initial value address port 3 data direction register p3ddr w h?0 h?fb4 port 3 data register p3dr r/w h?0 h?fb6 port 3 data direction register (p3ddr)??fb4 p3ddr is an 8-bit register that selects the direction of each pin in port 3. a pin functions as an output pin if the corresponding bit in p3ddr is set to ?,?and as an input pin if the bit is cleared to ?. port 3 data register (p3dr)??fb6 p3dr is an 8-bit register containing the data for pins p3 7 to p3 0 . when the cpu reads p3dr, for output pins it reads the value in the p3dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p3dr latch. mos pull-ups: are available for input pins in mode 3 when the dual-port ram is disabled. software can turn on the mos pull-up on by writing a ??in p3dr, and turn it off by writing a ?. bit 7 6 5 4 3 2 1 0 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 85 the mos pull-ups cannot be used in slave mode (when the dual-port ram is enabled). p3dr should be cleared to h'00 (its initial value) in slave mode. modes 1 and 2: in the expanded modes, port 3 is automatically used as the data bus. the values in p3ddr and p3dr are ignored. mode 3: in the single-chip mode, when the dual-port ram enable (dpme) bit in the system control register is cleared to ?,?port 3 can be used as a general-purpose input/output port. when dpme is set to ?,?entering the slave mode, port 3 is used as the dual-port ram data bus (ddb 7 to ddb 0 ). p3dr should also be cleared to h'00 in slave mode. see section 12, ?ual-port ram?for further information. reset and hardware standby mode: a reset or entry to the hardware standby mode clears p3ddr and p3dr to all ?,?and clears the dpme bit to "0." in modes 1 and 2, all pins are placed in the data input (high-impedance) state. in mode 3 (single-chip mode), all pins are in the input state with the mos pull-ups off. software standby mode: in the software standby mode, p3ddr, p3dr, and the dpme bit remain in their previous state. in modes 1 and 2 and slave mode, all pins are placed in the data input (high-impedance) state. in mode 3 with the dual-port ram disabled, all pins remain in their previous input or output state. figure 5-3 shows a schematic diagram of port 3. 86 figure 5-3. port 3 schematic diagram p3 n r q d c reset r q d c reset internal data bus dual-port ram data bus mode 3 dpme mode 3 wp3d wp3 mode 1 or 2 rp3 external address write external address read cs oe cs we wp3d: write port 3 ddr wp3: write port 3 rp3: read port 3 n = 0 to 7 p3nddr p3ndr figure 5-3 cs we wp3d: write port 3 ddr wp3: write port 3 rp3: read port 3 n = 0 to 3 87 5.5 port 4 port 4 is an 8-bit input/output port that also provides the input and output pins for the 8-bit timers and the output pins for the pwm timers. the pin functions depend on control bits in the control registers of the timers. pins not used by the timers are available for general-purpose input/output. table 5-8 lists the pin functions, which are the same in both the expanded and single-chip modes. table 5-8. port 4 pin functions (modes 1 to 3) usage pin functions i/o port p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 timer tmci 0 tmo 0 tmri 0 tmci 1 tmo 1 tmri 1 pw 0 pw 1 see section 7, ?-bit timer module?and section 8, ?wm timer module?for details of the timer control bits. pins of port 4 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive a darlington pair. when used as input pins, they have programmable mos pull-ups. table 5-9 details the port 4 registers. table 5-9. port 4 registers name abbreviation read/write initial value address port 4 data direction register p4ddr w h?0 h?fb5 port 4 data register p4dr r/w h?0 h?fb7 port 4 data direction register (p4ddr)??fb5 p4ddr is an 8-bit register that selects the direction of each pin in port 4. a pin functions as an output pin if the corresponding bit in p4ddr is set to ?,?and as an input pin if the bit is cleared to ?. bit 7 6 5 4 3 2 1 0 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 88 port 4 data register (p4dr)??fb7 p4dr is an 8-bit register containing the data for pins p4 7 to p4 0 . when the cpu reads p4dr, for output pins (p4ddr = "1") it reads the value in the p4dr latch, but for input pins (p4ddr = "0"), it obtains the logic level directly from the pin, bypassing the p4dr latch. this also applies to pins used for timer input or output. mos pull-ups: are available for input pins, including timer input pins, in all modes. software can turn the mos pull-up on by writing a ??in p4dr, and turn it off by writing a ?. pins p4 0 , p4 2 , p4 3 , and p4 5 : as indicated in table 5-8, these pins can be used for general-purpose input or output, or input of 8-bit timer clock and reset signals. when a pin is used for timer signal input, its p4ddr bit should normally be cleared to "0;" otherwise the timer will receive the value in p4dr. if input pull-up is not desired, the p4dr bit should also be cleared to "0." pins p4 1 , p4 4 , p4 6 , and p4 7 : as indicated in table 5-8, these pins can be used for general-purpose input or output, or for 8-bit timer output (p4 1 and p4 4 ) or pwm timer output (p4 6 and p4 7 ). pins used for timer output are unaffected by the values in p4ddr and p4dr, and their mos pull-ups are automatically turned off. reset and hardware standby mode: a reset or entry to the hardware standby mode clears p4ddr and p4dr to all ?? and makes all pins into input port pins with the mos pull-ups off. software standby mode: in the software standby mode, the control registers of the 8-bit and pwm timers are initialized but p4ddr and p4dr remain in their previous states. all pins become input or output port pins depending on the setting of p4ddr. output pins output the values in p4dr. the mos pull-ups of input pins are on or off depending on the values in p4dr. figures 5-4 and 5-5 show schematic diagrams of port 4. bit 7 6 5 4 3 2 1 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 89 figure 5-4. port 4 schematic diagram (pins p4 0 , p4 2 , p4 3 , and p4 5 ) p4 n r q d c r q d c internal data bus reset wp4 reset wp4d p4n ddr p4n dr rp4 wp4d: write port 4 ddr wp4: write port 4 rp4: read port 4 n = 0, 2, 3, 5 8-bit timer module counter clock input counter reset input 90 figure 5-5. port 4 schematic diagram (pins p4 1 , p4 4 , p4 6 , and p4 7 ) 5.6 port 5 port 5 is a 3-bit input/output port that also provides the input and output pins for asynchronous serial communication. the pin functions depend on control bits in the serial control register (scr). pins not used for serial communication are available for general-purpose input/output. table 5-10 lists the pin functions, which are the same in both the expanded and single-chip modes. table 5-10. port 5 pin functions (modes 1 to 3) usage pin functions i/o port p5 0 p5 1 p5 2 timer atxd arxd asck p4 n r q d c r q d c reset wp4 reset wp4d p4n ddr p4n dr rp4 wp4d: write port 4 ddr wp4: write port 4 rp4: read port 4 n = 1, 4, 6, 7 8-bit timer module, pwm timer module output enable 8-bit timer output or pwm timer output internal data bus 91 see section 9, ?erial communication interface?for details of the serial control bits. pins used by the serial communication interface are switched between input and output without regard to the values in the data direction register. pins of port 5 can drive a single ttl load and a 30pf capacitive load when they are used as output pins. they can also drive a darlington pair. when used as input pins, they have programmable mos pull-ups. table 5-11 details the port 5 registers. table 5-11. port 5 registers name abbreviation read/write initial value address port 5 data direction register p5ddr w h?8 h?fb8 port 5 data register p5dr r/w h?8 h?fba port 5 data direction register (p5ddr)??fb8 p5ddr is an 8-bit register that selects the direction of each pin in port 5. a pin functions as an output pin if the corresponding bit in p5ddr is set to ?,?and as an input pin if the bit is cleared to ?. port 5 data register (p5dr)??fba p5dr is an 8-bit register containing the data for pins p5 2 to p5 0 . when the cpu reads p5dr, for output pins (p5ddr = "1") it reads the value in the p5dr latch, but for input pins (p5ddr = "0"), it obtains the logic level directly from the pin, bypassing the p5dr latch. this also applies to pins bit 7 6 5 4 3 2 1 0 p5 2 ddr p5 1 ddr p5 0 ddr initial value 1 1 1 1 1 0 0 0 read/write w w w bit 7 6 5 4 3 2 1 0 p5 2 p5 1 p5 0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w 92 used for serial communication. mos pull-ups: are available for input pins, including serial communication input pins. software can turn the mos pull-up on by writing a ??in p5dr, and turn it off by writing a ?. pin p5 0 : this pin can be used for general-purpose input or output, or for output of asynchronous serial transmit data (atxd). when used for atxd output, this pin is unaffected by the values in p5ddr and p5dr, and its mos pull-up is automatically turned off. pin p5 1 : this pin can be used for general-purpose input or output, or for input of asynchronous serial receive data (arxd). when used for arxd input, this pin is unaffected by p5ddr and p5dr, except that software can turn on its mos pull-up by clearing its data direction bit to "0" and setting its data bit to "1." pin p5 2 : this pin can be used for general-purpose input or output, or for asynchronous serial clock input or output (asck). when used for asck input or output, this pin is unaffected by p5ddr and p5dr, except that software can turn on its mos pull-up by clearing its data direction bit to "0" and setting its data bit to "1." for asck usage, the mos pull-up should be turned off. reset and hardware standby mode: a reset or entry to the hardware standby mode makes all pins of port 5 into input port pins with the mos pull-ups off. software standby mode: in the software standby mode, the serial control register is initialized but p5ddr and p5dr remain in their previous states. all pins become input or output port pins depending on the setting of p5ddr. output pins output the values in p5dr. the mos pull-ups of input pins are on or off depending on the values in p5dr. figures 5-6 to 5-8 show schematic diagrams of port 5. 93 figure 5-6. port 5 schematic diagram (pin p5 0 ) p5 0 r q d c r q d c reset wp5 reset wp5d p5 0 ddr p5 0 dr rp5 wp5d: write port 5 ddr wp5: write port 5 rp5: read port 5 sci module asynchronous serial transmit enable asynchronous serial transmit data internal data bus 94 figure 5-7. port 5 schematic diagram (pin p5 1 ) p5 1 r q d c r q d c internal data bus reset wp5 reset wp5d p5 1 ddr p5 1 dr rp5 wp5d: write port 5 ddr wp5 write port 5 rp5: read port 5 sci module asynchronous serial receive enable asynchronous serial receive data 95 figure 5-8. port 5 schematic diagram (pin p5 2 ) 5.7 port 6 port 6 is an 8-bit input/output port that also provides the input and output pins for the free-running timer and the irq 6 and irq 7 input/output pins. the pin functions depend on control bits in the free-running timer control registers, and on bit 6 or 7 of the interrupt enable register. pins not used for timer or interrupt functions are available for general-purpose input/output. table 5-12 lists the pin functions, which are the same in both the expanded and single-chip modes. table 5-12. port 6 pin functions usage pin functions (modes 1 to 3) i/o port p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 timer/interrupt ftci ftoa ftia ftib ftic ftid ftob/irq 6 irq 7 r q d c r q d internal data bus reset wp5 reset wp5d p5 2 ddr p5 2 dr rp5 sci module asynchronous serial clock input enable asynchronous serial clock input asynchronous serial clock output enable asynchronous serial clock output wp5d: write port 5 ddr wp5 write port 5 rp5: read port 5 p5 2 96 see section 4 ?xception handling?and section 6, ?ree-running timer module?for details of the free-running timer and interrupts. pins of port 6 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive a darlington pair. when they are used as input pins, they have programmable mos pull-ups. table 5-13 details the port 6 registers. table 5-13. port 6 registers name abbreviation read/write initial value address port 6 data direction register p6ddr w h?0 h?fb9 port 6 data register p6dr r/w h?0 h?fbb port 6 data direction register (p6ddr)??fb9 p6ddr is an 8-bit register that selects the direction of each pin in port 6. a pin functions as an output pin if the corresponding bit in p6ddr is set to ?,?and as an input pin if the bit is cleared to ?. port 6 data register (p6dr)??fbb p6dr is an 8-bit register containing the data for pins p6 7 to p6 0 . when the cpu reads p6dr, for output pins (p6ddr = "1") it reads the value in the p6dr latch, but for input pins (p6ddr = "0"), it obtains the logic level directly from the pin, bypassing the p6dr latch. this also applies to pins used for input and output of timer and interrupt signals. bit 7 6 5 4 3 2 1 0 p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 97 mos pull-ups: are available for input pins, including pins used for input of timer or interrupt signals. software can turn the mos pull-up on by writing a ??in p6dr, and turn it off by writing a ?. pins p6 0 , p6 2 , p6 3 , p6 4 and p6 5 : as indicated in table 5-12, these pins can be used for general- purpose input or output, or for input of free-running timer clock and input capture signals. when a pin is used for free-running timer input, its p6ddr bit should be cleared to "0;" otherwise the free- running timer will receive the value in p6dr. if input pull-up is not desired, the p6dr bit should also be cleared to "0." pin p6 1 : this pin can be used for general-purpose input or output, or for the output compare a signal (ftoa) of the free-running timer. when used for ftoa output, this pin is unaffected by the values in p6ddr and p6dr, and its mos pull-up is automatically turned off. pin p6 6 : this pin can be used for general-purpose input or output, for the output compare b signal (ftob) of the free-running timer, or for irq 6 input. when used for ftob output, this pin is unaffected by the values in p6ddr and p6dr, and its mos pull-up is automatically turned off. when this pin is used for irq 6 input, p6 6 ddr should normally be cleared to "0," so that the value in p6dr will not generate interrupts. pin p6 7 : this pin can be used for general-purpose input or output, or irq 7 input. when it is used for irq 7 input, p6 7 ddr should normally be cleared to "0," so that the value in p6dr will not generate interrupts. reset and hardware standby mode: a reset or entry to the hardware standby mode clears p6ddr and p6dr to all ?? and makes all pins into input port pins with the mos pull-ups off. software standby mode: in the software standby mode, the free-running timer control registers are initialized but p6ddr and p6dr remain in their previous states. all pins become input or output port pins depending on the setting of p6ddr. output pins output the values in p6dr. the mos pull-ups of input pins are on or off depending on the values in p6dr. figures 5-9 to 5-11 shows schematic diagrams of port 6. 98 figure 5-9. port 6 schematic diagram (pins p6 0 , p6 2 , p6 3 , p6 4 , and p6 5 ) p6 n r q d c r q d c reset wp6 reset wp6d p6n ddr p6n dr rp6 wp6d: write port 6 ddr wp6: write port 6 rp6: read port 6 n = 0. 2 ?5 free-running timer module input capture input, counter clock input figure 5-9 internal data bus 99 figure 5-10. port 6 schematic diagram (pin p6 1 ) p6 1 r q d c r q d c reset wp6 reset wp6d p6 1 ddr p6 1 dr rp6 wp6d: write port 6 ddr wp6: write port 6 rp6: read port 6 free-running timer module output enable output-compare output internal data bus 100 figure 5-11. port 6 schematic diagram (pin p6 6 ) p6 6 r q d c r q d c reset wp6 reset wp6d p6 6 dr rp6 free-running timer module output enable output-compare output irq 6 input irq enable register irq 6 enable internal data bus wp6d: write port 6 ddr wp6: write port 6 rp6: read port 6 p6 6 ddr 101 figure 5-12. port 6 schematic diagram (pin p6 7 ) 5.8 port 7 port 7 is an 8-bit input port that also provides the analog input pins for the a/d converter module. the pin functions are the same in both the expanded and single-chip modes. table 5-14 lists the pin functions. table 5-15 describes the port 7 data register, which simply consists of connections of the port 7 pins to the internal data bus. figure 5-13 shows a schematic diagram of port 7. p6 7 r q d c r q d c internal data bus reset wp6 reset wp6d p6 7 ddr p6 7 dr rp6 irq enable register irq 7 enable irq 7 input wp6d: write port 6 ddr wp6: write port 6 rp6: read port 6 102 table 5-14. port 7 pin functions (modes 1 to 3) usage pin functions i/o port p7 0 p7 1 p7 2 p7 3 p7 4 p7 5 p7 6 p7 7 analog input an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 table 5-15. port 7 register name abbreviation read/write initial value address port 7 data register p7dr r undetermined h?fbe port 7 data register (p7dr)??fbe * depends on the levels of pins p7 7 to p7 0 . figure 5-13. port 7 schematic diagram bit 7 6 5 4 3 2 1 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value * * * * * * * * read/write r r r r r r r r p7 n rp7 rp7: read port 7 n = 0 to 7 a/d converter module analog input internal data bus figure 5-13 103 5.9 port 8 port 8 is a 7-bit input/output port that also provides pins for e clock output, dual-port ram register select input, interrupt input, and clock-synchronized serial communication. table 5-16 lists the pin functions. table 5-16. port 8 pin functions auxiliary functions i/o port expanded modes single-chip mode p8 0 input/output e clock output rs0 input p8 1 input/output ios output rs1 input p8 2 input/output rs2 input p8 3 input/output rs3 input p8 4 input/output ctxd output /irq 3 input p8 5 input/output crxd input /irq 4 input p8 6 input/output csck input/output /irq 5 input pins of port 8 can drive a single ttl load and a 30pf capacitive load when they are used as output pins. they can also drive a darlington pair. when used as input pins, they have programmable mos pull-ups. table 5-17 details the port 8 registers. table 5-17. port 8 registers name abbreviation read/write initial value address port 8 data direction register p8ddr w h?1 (modes 1 and 2) h?fbd h?0 (mode 3) port 8 data register p8dr r/w h'80 h?fbf 104 port 8 data direction register (p8ddr)??fbd p8ddr is an 8-bit register that selects the direction of each pin in port 8. a pin functions as an output pin if the corresponding bit in p8ddr is set to ?,?and as in input pin if the bit is cleared to ?. bit 7 is reserved. it cannot be modified, and is always read as "1." port 8 data register (p8dr)??fbf p8dr is an 8-bit register containing the data for pins p8 6 to p8 0 . when the cpu reads p8dr, for output pins (p8ddr = "1") it reads the value in the p8dr latch, but for input pins (p8ddr = "0"), it obtains the logic level directly from the pin, bypassing the p8dr latch. this also applies to pins used for dual-port ram register select input, interrupt input, serial communication, and e clock or ios output. bit 7 is reserved. it cannot be modified, and is always read as "1." mos pull-ups: are available for input pins in all modes, including pins used for dual-port ram register select input, interrupt input, or serial communication input. software can turn the mos pull-up on by writing a ??in p8dr, and turn it off by writing a ?. bit 7 6 5 4 3 2 1 0 p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr modes 1 and 2 initial value 1 0 0 0 0 0 0 1 read/write w w w w w w w mode 3 initial value 1 0 0 0 0 0 0 0 read/write w w w w w w w bit 7 6 5 4 3 2 1 0 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 initial value 1 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w 105 pin p8 0 : in modes 1 and 2 (expanded modes), pin p8 0 is used for e clock output if p8 0 ddr is set to "1," and for general-purpose input if p8 0 ddr is cleared ?.? it cannot be used for general- purpose output. in mode 3 (single-chip mode), when the dual-port ram is disabled (dpme = "0"), pin p8 0 can be used for general-purpose input or output. in the slave mode (dpme = "1"), this pin is used for register select input (rs0). in slave mode this pin is unaffected by the values in p8ddr and p8dr, except that software can turn on its mos pull-up by clearing its data direction bit to "0" and setting its data bit to "1." pin p8 1 : in modes 1 and 2 (expanded modes), pin p8 1 is used for ios output if p8 1 ddr is set to "1," and for general-purpose input if p8 1 ddr is cleared ?.? it cannot be used for general-purpose output. in mode 3, when the dual-port ram is disabled (dpme = "0"), pin p8 1 can be used for general- purpose input or output. in the slave mode (dpme = "1"), this pin is used for register select input (rs1). in slave mode this pin is unaffected by the values in p8ddr and p8dr, except that software can turn on its mos pull-up by clearing its data direction bit to "0" and setting its data bit to "1." pins p8 2 and p8 3 : these pins are available for general-purpose input or output in modes 1 and 2, and in mode 3 if the dual-port ram is disabled (dpme = "0"). in the slave mode (mode 3 with dpme = "1"), these pins are used for register select input (rs2 and rs3). they are unaffected by the bits in p8ddr and p8dr, except that software can turn on their mos pull-ups by clearing the p8ddr bit to "0" and setting the p8dr bit to "1." pin p8 4 : this pin has the same functions in all modes. it can be used for general-purpose input or output, for output of clock-synchronized serial transmit data (ctxd), or for irq 3 input. when used for ctxd output, this pin is unaffected by the values in p8ddr and p8dr, and its mos pull- up is automatically turned off. when this pin is used for irq 3 input, p8 4 ddr should normally be cleared to "0," so that the value in p8dr will not generate interrupts. pin p8 5 : this pin has the same functions in all modes. it can be used for general-purpose input or output, for input of clock-synchronized serial receive data (crxd), or for irq 4 input. when used for crxd input, this pin is unaffected by the values in p8ddr and p8dr, except that software can turn on its mos pull-up by clearing its data direction bit to "0" and setting its data bit to "1." when this pin is used for irq 4 input, p8 5 ddr should normally be cleared to "0," so that the value in p8dr will not generate interrupts. 106 pin p8 6 : this pin has the same functions in all modes. it can be used for general-purpose input or output, for serial clock input or output (csck), or for irq 5 input. when this pin is used for irq 5 input, p8 6 ddr should normally be cleared to "0," so that the value in p8dr will not generate interrupts. when used for csck input or output, this pin is unaffected by the values in p8ddr and p8dr, except that software can turn on its mos pull-up by clearing its data direction bit to "0" and setting its data bit to "1." for csck usage, the mos pull-up should be turned off. reset: a reset clears bits p8 6 ddr to p8 1 ddr to ??and clears the dpme bit, serial control bits, and interrupt enable bits to ?,?making p8 6 to p8 1 into input port pins with the mos pull-ups off. in the expanded modes (modes 1 and 2), p8 0 ddr is initialized to ??and the p8 0 pin is used for e clock output. in the single-chip mode (mode 3), p8 0 ddr is initialized to ??and the p8 0 pin is used for port input. hardware standby mode: all pins are placed in the high-impedance state with the mos pull-ups off. software standby mode: in the software standby mode, the serial control register is initialized, but the dpme bit, the interrupt enable register, p8ddr, and p8dr remain in their previous states. pins that were being used for serial communication revert to general-purpose input or output, depending on the value in p8ddr. other pins remain in their previous state. output pins output the values in p8dr. e clock output is low. figures 5-14 to 5-19 show schematic diagrams of port 8. 107 figure 5-14. port 8 schematic diagram (pin p8 0 ) p8 0 r q d c r q d c internal data bus hardware standby mode 3 mode 1 or 2 reset wp8 mode 3 reset s wp8d rp8 wp8d: write port 8 ddr wp8: write port 8 rp8: read port 8 dpme mode 3 mode 1 or 2 e dual-port ram module register select input p8 dr 0 p8 ddr 0 108 figure 5-15. port 8 schematic diagram (pin p8 1 ) p8 1 r q d c r q d c internal data bus mode 3 mode 1 or 2 reset wp8 reset wp8d p8 1 ddr p8 1 dr rp8 wp8d: write port 8 ddr wp8: write port 8 rp8: read port 8 dpme mode 3 dual-port ram module register select input ios output 109 figure 5-16. port 8 schematic diagram (pins p8 2 and p8 3 ) p8 n r q d c r q d c reset wp8 reset wp8d p8 n ddr p8 n dr rp8 wp8d: write port 8 ddr wp8: write port 8 rp8: read port 8 n = 2, 3 dpme mode 3 dual-port ram module register select input internal data bus 110 figure 5-17. port 8 schematic diagram (pin p8 4 ) p8 4 r q d c r q d c reset wp8 reset wp8d p8 4 ddr p8 4 dr rp8 sci module synchronous serial transmit enable synchronous serial transmit data internal data bus irq 3 input irq enable register irq 3 enable wp8d: write port 8 ddr wp8: write port 8 rp8: read port 8 111 figure 5-18. port 8 schematic diagram (pin p8 5 ) p8 5 r q d c r q d c reset wp8 reset wp8d p8 5 ddr p8 5 dr rp8 sci module internal data bus irq 4 input irq enable register irq 4 enable synchronous serial input enable synchronous receive data wp8d: write port 8 ddr wp8: write port 8 rp8: read port 8 112 figure 5-19. port 8 schematic diagram (pin p8 6 ) r q d c r q d internal data bus reset wp8 reset wp8d p8 6 ddr p8 6 dr rp8 sci module synchronous serial clock input enable synchronous serial clock input synchronous serial clock output enable synchronous serial clock output irq 5 input irq enable register irq 5 enable wp8d: write port 8 ddr wp8: write port 8 rp8: read port 8 p8 6 c 113 5.10 port 9 port 9 is an 8-bit input/output port that also provides pins for interrupt input (irq 0 to irq 2 ), a/d trigger input, system clock ( ) output, bus control signals (in the expanded modes), and dual-port ram interface control signals (in the single-chip mode). pins p9 7 to p9 3 have different functions in different modes. pins p9 2 to p9 0 have the same functions in all modes. table 5-18 lists the pin functions. table 5-18. port 9 pin functions single-chip mode pin expanded modes dpme = 0 dpme = 1 p9 0 p9 0 input/output , irq 2 input, and adtrg input (simultaneously) p9 1 p9 1 input/output and irq 1 input (simultaneously) p9 2 p9 2 input/output and irq 0 input (simultaneously) p9 3 rd output p9 3 input/output cs input p9 4 wr output p9 4 input/output oe input p9 5 as output p9 5 input/output rdy output p9 6 output p9 6 input or output p9 6 input or output p9 7 wait input p9 7 input/output we input pins of port 9 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. when used as input pins, they have programmable mos pull-ups. table 5-19 details the port 9 registers. table 5-19. port 9 registers name abbreviation read/write initial value address port 9 data direction register p9ddr w h?0 (modes 1 and 2) h?fc0 h'00 (mode 3 port 9 data register p9dr r/w h?0 h?fc1 114 port 9 data direction register (p9ddr)??fc0 p9ddr is an 8-bit register that selects the direction of each pin in port 9. a pin functions as an output pin if the corresponding bit in p9ddr is set to ?,?and as in input pin if the bit is cleared to ?. port 9 data register (p9dr)??fc1 p9dr is an 8-bit register containing the data for pins p9 7 to p9 0 . when the cpu reads p9dr, for output pins (p9ddr = "1") it reads the value in the p9dr latch, but for input pins (p9ddr = "0"), it obtains the logic level directly from the pin, bypassing the p9dr latch. this also applies to pins used for interrupt input, a/d trigger input, clock output, and control signal input or output. mos pull-ups: are available for input pins, including pins used for input of interrupt request signals, the a/d trigger signal, and control signals. software can turn the mos pull-up on by writing a ??in p9dr, and turn it off by writing a ?. pins p9 0 , p9 1 , and p9 2 : can be used for general-purpose input or output, interrupt request input, or a/d trigger input. see table 5-18. if a pin is used for interrupt or a/d trigger input, its data direction bit should be cleared to "0," so that the output from p9dr will not generate an interrupt request or a/d trigger signal. pins p9 3 and p9 4 : in modes 1 and 2 (the expanded modes), these pins are used for output of the rd and wr bus control signals. they are unaffected by the values in p9ddr and p9dr, and their bit 7 6 5 4 3 2 1 0 p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr modes 1 and 2 initial value 0 1 0 0 0 0 0 0 read/write w w w w w w w mode 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 115 mos pull-ups are automatically turned off. in mode 3 (single-chip mode) with the dual-port ram disabled (dpme = "0"), these pins can be used for general-purpose input or output. in slave mode (mode 3 with dpme = "1"), these pins are used for input of the cs and oe dual-port ram interface control signals. they are unaffected by the values in p9ddr and p9dr, except that software can turn on their mos pull-ups by clearing their data direction bits to "0" and setting their data bits to "1." pin p9 5 : in modes 1 and 2 and slave mode, this pin is used for output of the as bus control signal or rdy dual-port ram interface control signal. it is unaffected by the values in p9ddr and p9dr, and its mos pull-up is automatically turned off. in mode 3 with the dual-port ram disabled (dpme = "0"), this pin can be used for general- purpose input or output. pin p9 6 : in modes 1 and 2, this pin is used for system clock ( ) output. its mos pull-up is automatically turned off. in mode 3, this pin is used for general-purpose input if p9 6 ddr is cleared to "0," or system clock output if p9 6 ddr is set to "1." pin p9 7 : in modes 1 and 2 and slave mode, this pin is used for input of the wait bus control signal or we dual-port ram interface control signal. it is unaffected by the values in p9ddr and p9dr, except that software can turn on its mos pull-up by clearing its data direction bit to "0" and setting its data bit to "1." in mode 3 (single-chip mode) with the dual-port ram disabled (dpme = "0"), this pin can be used for general-purpose input or output. reset: in the single-chip mode (mode 3), a reset initializes all pins of port 9 to the general-purpose input function with the mos pull-ups off. in the expanded modes (modes 1 and 2), p9 0 to p9 2 are initialized as input port pins, and p9 3 to p9 7 are initialized to their bus control and system clock output functions. hardware standby mode: all pins are placed in the high-impedance state with their mos pull- ups off. 116 software standby mode: all pins remain in their previous state. for rd, wr, as, and this means the high output state. figures 5-20 to 5-25 show schematic diagrams of port 9. figure 5-20. port 9 schematic diagram (pin p9 0 ) p9 0 r q d c r q d c internal data bus reset wp9 reset wp9d p9 0 ddr p9 0 dr rp9 adtrg irq 2 input irq enable register irq 2 enable a/d converter module wp8d: write port 8 ddr wp8: write port 8 rp8: read port 8 117 figure 5-21. port 9 schematic diagram (pins p9 1 to p9 2 ) p9 n r q d c r q d c internal data bus reset wp9 reset wp9d p9 n ddr p9 n dr rp9 irq enable register irq 0 enable irq 1 input irq 1 enable wp9d: write port 9 ddr wp9: write port 9 rp9: read port 9 n = 1, 2 irq 0 input figure 5-21 118 figure 5-22. port 9 schematic diagram (pins p9 3 and p9 4 ) p9 n r q d c r q d c internal data bus hardware standby mode 3 mode 1 or 2 reset wp9 reset wp9d p9n ddr p9n dr rp9 wp9d: write port 9 ddr wp9: write port 9 rp9: read port 9 n: 3, 4 dpme mode 3 dual-port ram module cs input oe input mode 1 or 2 rd output wr output 119 figure 5-23. port 9 schematic diagram (pin p9 5 ) p9 5 r q d c r q d c internal data bus hardware standby mode 1 or 2 reset wp9 reset wp9d p9 5 ddr p9 5 dr rp9 wp9d: write port 9 ddr wp9: write port 9 rp9: read port 9 * nmos open drain if dpme="1" (slave mode) dpme mode 3 mode 1 or 2 rdy output as output dual-port ram module * 120 figure 5-24. port 9 schematic diagram (pin p9 6 ) p9 6 r q d c internal data bus reset wp9 p9 6 dr wp9d: write port 9 ddr wp9: write port 9 rp9: read port 9 * set-priority r q d c mode1,2 reset s wp9d p9 6 ddr * rp9 hardware standby 121 figure 5-25. port 9 schematic diagram (pin p9 7 ) p9 7 r q d c r q d c internal data bus reset wp9 reset wp9d p9 7 ddr p9 7 dr rp9 wp9d: write port 9 ddr wp9: write port 9 rp9: read port 9 dpme mode 3 wait input dual-port ram module we input mode 1 or 2 122 section 6. 16-bit free-running timer 6.1 overview the h8/330 has an on-chip 16-bit free-running timer (frt) module that uses a 16-bit free-running counter as a time base. applications of the frt module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 6.1.1 features the features of the free-running timer module are listed below. selection of four clock sources the free-running counter can be driven by an internal clock source ( /2, /8, or /32), or an external clock input (enabling use as an external event counter). two independent comparators each comparator can generate an independent waveform. four input capture channels the current count can be captured on the rising or falling edge (selectable) of an input signal. the four input capture registers can be used separately, or in a buffer mode. counter can be cleared under program control the free-running counters can be cleared on compare-match a. seven independent interrupts compare-match a and b, input capture a to d, and overflow interrupts are requested independently. 6.1.2 block diagram figure 6-1 shows a block diagram of the free-running timer. 123 figure 6-1. block diagram of 16-bit free-running timer external clock source internal clock sources clock select comparator a ocra (h/l) comparator b ocrb (h/l) bus interface internal data bus /2 /8 /32 ftci compare- clear clock ftoa ftob overflow icra (h/l) match a compare- match b capture frc (h/l) tcsr ftia ftib ftic ftid control logic module data bus tier tcr tocr ocib ocia fovi interrupt signals icia icib icic icid frc: ocra, b: icra, b, c, d: tcsr: free-running counter (16 bits) output compare register a, b (16 bits) input capture register a, b, c, d (16 bits) timer control/status register (8 bits) tier: tcr: tocr: timer interrupt enable register (8 bits) timer control register (8 bits) timer output compare control register (8 bits) icrb (h/l) icrc (h/l) icrd (h/l) 124 6.1.3 input and output pins table 6-1 lists the input and output pins of the free-running timer module. table 6-1. input and output pins of free-running timer module 6.1.4 register configuration table 6-2 lists the registers of the free-running timer module. table 6-2. register configuration notes: * 1 software can write a ??to clear bits 7 to 1, but cannot write a ??in these bits. * 2 ocra and ocrb share the same addresses. access is controlled by the ocrs bit in tocr. name abbreviation i/o function counter clock input ftci input input of external free-running counter clock signal output compare a ftoa output output controlled by comparator a output compare b ftob output output controlled by comparator b input capture a ftia input trigger for capturing current count into input capture register a input capture b ftib input trigger for capturing current count into input capture register b input capture c ftic input trigger for capturing current count into input capture register c input capture d ftid input trigger for capturing current count into input capture register d initial name abbreviation r/w value address timer interrupt enable register tier r/w h?1 h?f90 timer control/status register tcsr r/(w)* 1 h?0 h?f91 free-running counter (high) frc (h) r/w h?0 h?f92 free-running counter (low) frc (l) r/w h?0 h?f93 output compare register a/b (high)* 2 ocra/b (h) r/w h?f h?f94 output compare register a/b (low)* 2 ocra/b (l) r/w h?f h?f95 timer control register tcr r/w h?0 h?f96 timer output compare control register tocr r/w h?0 h?f97 input capture register a (high) icra (h) r h?0 h?f98 input capture register a (low) icra (l) r h?0 h?f99 125 table 6-2. register configuration (cont.) 6.2 register descriptions 6.2.1 free-running counter (frc) ?h?f92 the frc is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. the clock source is selected by the clock select 1 and 0 bits (cks1 and cks0) of the timer control register (tcr). when the frc overflows from h?fff to h?000, the overflow flag (ovf) in the timer control/status register (tcsr) is set to ?. because the frc is a 16-bit register, a temporary register (temp) is used when the frc is written or read. see section 6.3, ?pu interface?for details. the frc is initialized to h?000 at a reset and in the standby modes. it can also be cleared by compare-match a. initial name abbreviation r/w value address input capture register b (high) icrb (h) r h?0 h?f9a input capture register b (low) icrb (l) r h?0 h?f9b input capture register c (high) icrc (h) r h?0 h?f9c input capture register c (low) icrc (l) r h?0 h?f9d input capture register d (high) icrd (h) r h?0 h?f9e input capture register d (low) icrd (l) r h?0 h?f9f bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value read/ r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w write 126 6.2.2 output compare registers a and b (ocra and ocrb) ?h?f94 ocra and ocrb are 16-bit readable/writable registers, the contents of which are continually compared with the value in the frc. when a match is detected, the corresponding output compare flag (ocfa or ocfb) is set in the timer control/status register (tcsr). in addition, if the output enable bit (oea or oeb) in the timer output compare control register (tocr) is set to ?,?when the output compare register and frc values match, the logic level selected by the output level bit (olvla or olvlb) in the tocr is output at the output compare pin (ftoa or ftob). ocra and ocrb share the same address. they are differentiated by the ocrs bit in the tocr. a temporary register (temp) is used for write access, as explained in section 6.3, "cpu interface." ocra and ocrb are initialized to h?fff at a reset and in the standby modes. 6.2.3 input capture registers a to d (icra to icrd) ?h?f98, h?f9a, h?f9c, h?f9e each input capture register is a 16-bit read-only register. when the rising or falling edge of the signal at an input capture pin (ftia to ftid) is detected, the current value of the frc is copied to the corresponding input capture register (icra to icrd). at the same time, the corresponding input capture flag (icfa to icfd) in the timer control/status register (tcsr) is set to ?.? the input capture edge is selected by the input edge select bits (iedga to iedgd) in the timer interrupt enable register (tier). bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 value read/ r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w write bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value read/ r r r r r r r r r r r r r r r r write 127 input capture can be buffered by using the input capture registers in pairs. when the bufea bit in the timer control register (tcr) is set to ?,?icrc is used as a buffer register for icra as shown in figure 6-2. when an ftia input is received, the old icra contents are moved into icrc, and the new frc count is copied into icra. figure 6-2. input capture buffering similarly, when the bufeb bit in tier is set to ?,?icrd is used as a buffer register for icrb. when input capture is buffered, if the two input edge bits are set to different values (iedga iedgc or iedgb iedgd), then input capture is triggered on both the rising and falling edges of the ftia or ftib input signal. if the two input edge bits are set to the same value (iedga = iedgc or iedgb = iedgd), then input capture is triggered on only one edge. because the input capture registers are 16-bit registers, a temporary register (temp) is used when they are read. see section 6.3, ?pu interface?for details. to ensure input capture, the width of the input capture pulse (ftia, ftib, ftic, ftid) should be at least 1.5 system clock periods (1.5). when triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. figure 6-3. minimum input capture pulse width bufea: iedga: iedgc: icrc: icra: frc: buffer enable a input edge select a input edge select c input capture register c input capture register a free-running counter bufea iedga iedgc ftia edge detect and capture signal generating circuit frc icrc icra ftia, ftib, ftic, or ftid 128 the input capture registers are initialized to h?000 at a reset and in the standby modes. note: when input capture is detected, the frc value is transferred to the input capture register even if the input capture flag is already set. 6.2.4 timer interrupt enable register (tier) ?h?f90 the tier is an 8-bit readable/writable register that enables and disables interrupts. the tier is initialized to h?1 (all interrupts disabled) at a reset and in the standby modes. bit 7 ?input capture interrupt a enable (iciae): this bit selects whether to request input capture interrupt a (icia) when input capture flag a (icfa) in the timer status/control register (tcsr) is set to ?. bit 6 ?input capture interrupt b enable (icibe): this bit selects whether to request input capture interrupt b (icib) when input capture flag b (icfb) in the timer status/control register (tcsr) is set to ?. bit 5 ?input capture interrupt c enable (icice): this bit selects whether to request input capture interrupt c (icic) when input capture flag c (icfc) in the timer status/control register (tcsr) is set to ?. bit 7 6 5 4 3 2 1 0 iciae icibe icice icide ociae ocibe ovie initial value 0 0 0 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w bit 7 iciae description 0 input capture interrupt request a (icia) is disabled. (initial value) 1 input capture interrupt request a (icia) is enabled. bit 6 icibe description 0 input capture interrupt request b (icib) is disabled. (initial value) 1 input capture interrupt request b (icib) is enabled. 129 bit 4 ?input capture interrupt d enable (icide): this bit selects whether to request input capture interrupt d (icid) when input capture flag d (icfd) in the timer status/control register (tcsr) is set to ?. bit 3 ?output compare interrupt a enable (ociae): this bit selects whether to request output compare interrupt a (ocia) when output compare flag a (ocfa) in the timer status/control register (tcsr) is set to ?. bit 2 ?output compare interrupt b enable (ocibe): this bit selects whether to request output compare interrupt b (ocib) when output compare flag b (ocfb) in the timer status/control register (tcsr) is set to ?. bit 1 ?timer overflow interrupt enable (ovie): this bit selects whether to request a free- running timer overflow interrupt (fovi) when the timer overflow flag (ovf) in the timer status/control register (tcsr) is set to ?. bit 5 icice description 0 input capture interrupt request c (icic) is disabled. (initial value) 1 input capture interrupt request c (icic) is enabled. bit 4 icide description 0 input capture interrupt request d (icid) is disabled. (initial value) 1 input capture interrupt request d (icid) is enabled. bit 3 ociae description 0 output compare interrupt request a (ocia) is disabled. (initial value) 1 output compare interrupt request a (ocia) is enabled. bit 2 ocibe description 0 output compare interrupt request b (ocib) is disabled. (initial value) 1 output compare interrupt request b (ocib) is enabled. 130 bit 0 ?reserved: this bit cannot be modified and is always read as ?. 6.2.5 timer control/status register (tcsr) ?h?f91 the tcsr is an 8-bit readable and partially writable* register contains the seven interrupt flags and specifies whether to clear the counter on compare-match a (when the frc and ocra values match). * software can write a ??in bits 7 to 1 to clear the flags, but cannot write a ??in these bits. the tcsr is initialized to h?0 at a reset and in the standby modes. bit 7 ?input capture flag a (icfa): this status bit is set to ??to flag an input capture a event. if bufea = ?,?icfa indicates that the frc value has been copied to icra. if bufea = ?,?icfa indicates that the old icra value has been moved into icrc and the new frc value has been copied to icra. icfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1 ovie description 0 timer overflow interrupt request (fovi) is disabled. (initial value) 1 timer overflow interrupt request (fovi) is enabled. bit 7 6 5 4 3 2 1 0 icfa icfb icfc icfd ocfa ocfb ovf cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/w bit 7 icfa description 0 to clear icfa, the cpu must read icfa after it (initial value) has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when an ftia input signal causes the frc value to be copied to icra. 131 bit 6 ?input capture flag b (icfb): this status bit is set to ??to flag an input capture b event. if bufeb = ?,?icfb indicates that the frc value has been copied to icrb. if bufeb = ?,?icfb indicates that the old icrb value has been moved into icrd and the new frc value has been copied to icrb. icfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5 ?input capture flag c (icfc): this status bit is set to ??to flag input of a rising or falling edge of ftic as selected by the iedgc bit. when bufea = ?,?this indicates capture of the frc count in icrc. when bufea = ?,?however, the frc count is not captured, so icfc becomes simply an external interrupt flag. in other words, the buffer mode frees ftic for use as a general-purpose interrupt signal (which can be enabled or disabled by the icice bit). icfc must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4 ?input capture flag d (icfd): this status bit is set to ??to flag input of a rising or falling edge of ftid as selected by the iedgd bit. when bufeb = ?,?this indicates capture of the frc count in icrd. when bufeb = ?,?however, the frc count is not captured, so icfd becomes simply an external interrupt flag. in other words, the buffer mode frees ftid for use as a general-purpose interrupt signal (which can be enabled or disabled by the icide bit). icfd must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6 icfb description 0 to clear icfb, the cpu must read icfb after it (initial value) has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when an ftib input signal causes the frc value to be copied to icrb. bit 5 icfc description 0 to clear icfc, the cpu must read icfc after it (initial value) has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when an ftic input signal is received. 132 bit 3 ?output compare flag a (ocfa): this status flag is set to ??when the frc value matches the ocra value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 2 ?output compare flag b (ocfb): this status flag is set to ??when the frc value matches the ocrb value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1 ?timer overflow flag (ovf): this status flag is set to ??when the frc overflows (changes from h?fff to h?000). this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4 icfd description 0 to clear icfd, the cpu must read icfd after it (initial value) has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when an ftid input signal is received. bit 3 ocfa description 0 to clear ocfa, the cpu must read ocfa after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when frc = ocra. bit 2 ocfb description 0 to clear ocfb, the cpu must read ocfb after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when frc = ocrb. bit 1 ovf description 0 to clear ovf, the cpu must read ovf after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when frc changes from h?fff to h?000. 133 bit 0 ?counter clear a (cclra): this bit selects whether to clear the frc at compare-match a (when the frc and ocra values match). 6.2.6 timer control register (tcr) ?h?f96 the tcr is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the frc clock source. the tcr is initialized to h?0 at a reset and in the standby modes. bit 7 ?input edge select a (iedga): this bit causes input capture a events to be recognized on the selected edge of the input capture a signal (ftia). bit 6 ?input edge select b (iedgb): this bit causes input capture b events to be recognized on the selected edge of the input capture b signal (ftib). bit 0 cclra description 0 the frc is not cleared. (initial value) 1 the frc is cleared at compare-match a. bit 7 6 5 4 3 2 1 0 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 iedga description 0 input capture a events are recognized on the falling edge of ftia. (initial value) 1 input capture a events are recognized on the rising edge of ftia. bit 6 iedgb description 0 input capture b events are recognized on the falling edge of ftib. (initial value) 1 input capture b events are recognized on the rising edge of ftib. 134 bit 5 ?input edge select c (iedgc): this bit causes input capture c events to be recognized on the selected edge of the input capture c signal (ftic). in buffer mode (when bufea = ??, it also causes input capture a events to be recognized on the selected edge of ftia. bit 4 ?input edge select d (iedgd): this bit causes input capture d events to be recognized on the selected edge of the input capture d signal (ftid). in the buffer mode (when bufeb = ??, it also causes input capture b events to be recognized on the selected edge of ftib. bit 3 ?buffer enable a (bufea): this bit selects whether to use icrc as a buffer register for icra. bit 2 ?buffer enable b (bufeb): this bit selects whether to use icrd as a buffer register for icrb. bits 1 and 0 ?clock select (cks1 and cks0): these bits select external clock input or one of three internal clock sources for the frc. external clock pulses are counted on the rising edge. bit 5 iedgc description 0 input capture c events are recognized on the falling edge of ftic. (initial value) 1 input capture c events are recognized on the rising edge of ftic. bit 4 iedgd description 0 input capture d events are recognized on the falling edge of ftid. (initial value) 1 input capture d events are recognized on the rising edge of ftid. bit 3 bufea description 0 icrc is used for input capture c. (initial value) 1 icrc is used as a buffer register for input capture a. input c is not captured. bit 2 bufeb description 0 icrd is used for input capture d. (initial value) 1 icrd is used as a buffer register for input capture b. input d is not captured. 135 6.2.7 timer output compare control register (tocr) ?h?f97 the tocr is an 8-bit readable/writable register that controls the output compare function. the tocr is initialized to h?0 at a reset and in the standby modes. bits 7 to 5 ?reserved: these bits cannot be modified and are always read as ?. bit 4 ?output compare register select (ocrs): when the cpu accesses addresses h?f94 and h?f95, this bit directs the access to either ocra or ocrb. these two registers share the same addresses as follows: upper byte of ocra and upper byte of ocrb: h?f94 lower byte of ocra and lower byte of ocrb: h?f95 bit 3 ?output enable a (oea): this bit enables or disables output of the output compare a signal (ftoa). when output compare a is disabled, the corresponding pin is used as a general- purpose input/output port. bit 1 bit 0 cks1 cks0 description 0 0 /2 internal clock source (initial value) 0 1 /8 internal clock source 1 0 /32 internal clock source 1 1 external clock source (rising edge) bit 7 6 5 4 3 2 1 0 ocrs oea oeb olvla olvlb initial value 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w bit 4 ocrs description 0 the cpu can access ocra. (initial value) 1 the cpu can access ocrb. bit 3 oea description 0 output compare a output is disabled. (initial value) 1 output compare a output is enabled. 136 bit 2 ?output enable b (oeb): this bit enables or disables output of the output compare b signal (ftob). when output compare b is disabled, the corresponding pin is used as a general- purpose input/output or interrupt port. bit 1 ?output level a (olvla): this bit selects the logic level to be output at the ftoa pin when the frc and ocra values match. bit 0 ?output level b (olvlb): this bit selects the logic level to be output at the ftob pin when the frc and ocrb values match. 6.3 cpu interface the free-running counter (frc), output compare registers (ocra and ocrb), and input capture registers (icra to icrd) are 16-bit registers, but they are connected to an 8-bit data bus. when the cpu accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (temp). these registers are written and read as follows: register write when the cpu writes to the upper byte, the byte of write data is placed in temp. next, when the cpu writes to the lower byte, this byte of data is combined with the byte in temp and all 16 bits are written in the register simultaneously. bit 2 oeb description 0 output compare b output is disabled. (initial value) 1 output compare b output is enabled. bit 1 olvla description 0 a ??logic level (low) is output for compare-match a. (initial value) 1 a ??logic level (high) is output for compare-match a. bit 0 olvlb description 0 a ??logic level (low) is output for compare-match b. (initial value) 1 a ??logic level (high) is output for compare-match b. 137 register read when the cpu reads the upper byte, the upper byte of data is sent to the cpu and the lower byte is placed in temp. when the cpu reads the lower byte, it receives the value in temp. (as an exception, when the cpu reads ocra or ocrb, it reads both the upper and lower bytes directly, without using temp.) programs that access these registers should normally use word access. equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. data will not be transferred correctly if the bytes are accessed in reverse order, if only one byte is accessed, or if the upper and lower bytes are accessed separately and another register is accessed in between, altering the value in temp. coding examples to write the contents of general register r0 to ocra: mov.w r0, @ocra to transfer the contents of icra to general register r0: mov.w @icra, r0 figure 6-4 shows the data flow when the frc is accessed. the other registers are accessed in the same way. figure 6-4 (a). write access to frc (when cpu writes h?a55) module data bus (1) upper byte write bus interface cpu writes data h?a frc h [ ] frc l [ ] temp [h?a] (2) lower byte write bus interface module data bus cpu writes data h?5 temp [h?a] frc h [h?a] frc l [h?5] 138 figure 6-4 (b). read access to frc (when frc contains h?a55) 6.4 operation 6.4.1 frc incrementation timing the frc increments on a pulse generated once for each period of the selected (internal or external) clock source. the internal clock sources are created from the system clock ( ) by a prescaler. the frc increments on a pulse generated from the falling edge of the prescaler output. see figure 6-5. (1) upper byte read bus interface module data bus cpu writes data h?a temp [h?5] frc h [h?a] frc l [h?5] (2) lower byte read bus interface module data bus cpu writes data h?5 temp [h?5] frc h [ ] frc l [ ] 139 figure 6-5. increment timing for internal clock source if external clock input is selected, the frc increments on the rising edge of the ftci clock signal. figure 6-6 shows the increment timing. the pulse width of the external clock signal must be at least 1.5 system clock ( ) periods. the counter will not increment correctly if the pulse width is shorter than one period. figure 6-6. increment timing for external clock source figure 6-7. minimum external clock pulse width prescaler output frc clock pulse frc n ?1 n n + 1 n n + 1 ftci frc frc clock pulse ftci 140 6.4.2 output compare timing (1) setting of output compare flags a and b (ocfa and ocfb): the output compare flags are set to ??by an internal compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before the frc increments to a new value. accordingly, when the frc and ocr values match, the compare-match signal is not generated until the next period of the clock source. figure 6-8 shows the timing of the setting of the output compare flags. figure 6-8. setting of output compare flags (2) timing of output compare flag (ocfa or ocfb) clearing: the output compare flag ocfa or ocfb is cleared when the cpu writes a ??in this bit. figure 6-9. clearing of output compare flag n n n + 1 frc ocr internal compare- match signal ocfa or ocfb ocra or ocrb ocfa or ocfb write cycle: cpu writes "0" in ocfa or ocfb t 1 t 2 t 3 figure 6-9 141 (3) output timing: when a compare-match occurs, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). figure 6- 10 shows the timing of this operation for compare-match a. figure 6-10. timing of output compare a (4) frc clear timing: if the cclra bit in the tcsr is set to ?,?the frc is cleared when compare-match a occurs. figure 6-11 shows the timing of this operation. figure 6-11. clearing of frc by compare-match a 6.4.3 input capture timing (1) input capture timing: an internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin ftix (x = a, b, c, d), as selected by the corresponding iedgx bit in tcr. figure 6-12 shows the usual input capture timing when the rising edge is selected (iedgx = ??. internal compare- match a signal olvla ftoa * cleared by software frc ocra n n n n + 1 clear * n n + 1 figure 6-10 internal compare- match a signal frc n h'0000 142 figure 6-12. input capture timing (usual case) if the upper byte of icrx is being read when the input capture signal arrives, the internal input capture signal is delayed by one state. figure 6-13 shows the timing for this case. figure 6-13. input capture timing (1-state delay) in buffer mode, this delay occurs if the cpu is reading either of the two registers concerned. when icra and icrc are used in buffer mode, for example, if the upper byte of either icra or icrc is being read when the ftia input arrives, the internal input capture signal is delayed by one state. figure 6-14 shows the timing for this case. the case of icrb and icrd is similar. figure 6-14. input capture timing (1-state delay, buffer mode) input at fti pin internal input capture signal read cycle: cpu reads upper byte of icr t 1 t 2 t 3 input at fti pin internal input capture signal figure 6-13 t t t read cycle: cpu reads upper byte of icra or icrc input at ftia pin internal input capture signal 1 2 3 figure 6-14 143 figure 6-15 shows how input capture operates when icra and icrc are used in buffer mode and iedga and iedgc are set to different values (iedga = 0 and iedgc = 1, or iedga = 1 and iedgc = 0), so that input capture is performed on both the rising and falling edges of ftia. figure 6-15. buffered input capture with both edges selected in this mode, ftic does not cause the frc contents to be copied to icrc. however, input capture flag c still sets on the edge of ftic selected by iedgc, and if the interrupt enable bit (icice) is set, a cpu interrupt is requested. the situation when icrb and icrd are used in buffer mode is similar. (2) timing of input capture flag (icf) setting: the input capture flag icfx (x = a, b, c, d) is set to ??by the internal input capture signal. figure 6-16 shows the timing of this operation. figure 6-16. setting of input capture flag internal input capture signal icf frc icr n n n n + 1 n n + 1 n a a b n n n a ftia internal input capture signal frc icra icrc 144 (3) timing of input capture flag (icf) clearing: the input capture flag icfx (x = a, b, c, d) is cleared when the cpu writes a ??in this bit. figure 6-17. clearing of input capture flag 6.4.4 setting of frc overflow flag (ovf) the frc overflow flag (ovf) is set to ??when the frc overflows (changes from h?fff to h?000). figure 6-18 shows the timing of this operation. figure 6-18. setting of overflow flag (ovf) (2) timing of overflow flag (ovf) clearing: the overflow flag is cleared when the cpu writes a ??in this bit. figure 6-19. clearing of overflow flag t t t icfx write cycle: cpu writes "0" in icfx 1 2 3 figure 6-17 ovf frc internal overflow signal h'ffff h'0000 ovf write cycle: cpu writes "0" in ovf t 1 t 2 t 3 figure 6-19 145 6.5 interrupts the free-running timer channel can request seven types of interrupts: input capture a to d (icia, icib, icic, icid), output compare a and b (ocia and ocib), and overflow (fovi). each interrupt is requested when the corresponding enable and flag bits are set. independent signals are sent to the interrupt controller for each type of interrupt. table 6-3 lists information about these interrupts. table 6-3. free-running timer interrupts 6.6 sample application in the example below, the free-running timer channel is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship. the programming is as follows: (1) the cclra bit in the tcsr is set to ?. (2) each time a compare-match interrupt occurs, software inverts the corresponding output level bit in tocr (olvla or olvlb). figure 6-20. square-wave output (example) interrupt description priority icia requested when icfa and iciae are set high icib requested when icfb and icibe are set icic requested when icfc and icice are set icid requested when icfd and icide are set ocia requested when ocfa and ociae are set ocib requested when ocfb and ocibe are set fovi requested when ovf and ovie are set low frc h?fff ocra ocrb h?000 ftoa ftob clear counter 146 6.7 application notes application programmers should note that the following types of contention can occur in the free- running timers. (1) contention between frc write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. figure 6-21 shows this type of contention. figure 6-21. frc write-clear contention (2) contention between frc write and increment: if an frc increment pulse is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and the frc is not incremented. figure 6-22 shows this type of contention. write cycle: cpu write to lower byte of frc frc address n h'0000 t 1 t 2 t 3 internal address bus internal write signal frc clear signal frc figure 6-21 147 figure 6-22. frc write-increment contention (3) contention between ocr write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to the lower byte of ocra or ocrb, the write takes precedence and the compare-match signal is inhibited. figure 6-23 shows this type of contention. write cycle: cpu write to lower byte of frc frc address internal address bus internal write signal frc clock pulse frc n m t t t write data 1 2 3 figure 6-22 148 figure 6-23. contention between ocr write and compare-match (4) incrementation caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause the frc to increment. this depends on the time at which the clock select bits (cks1 and cks0) are rewritten, as shown in table 6-4. the pulse that increments the frc is generated at the falling edge of the internal clock source. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 6-5, the changeover generates a falling edge that triggers the frc increment clock pulse. switching between an internal and external clock source can also cause the frc to increment. write cycle: cpu write to lower byte of ocra or ocrb ocr address n n + 1 n m inhibited write data internal address bus internal write signal compare-match a or b signal ocra or ocrb frc t 1 t t 2 3 149 table 6-4. effect of changing internal clock sources * the switching of clock sources is regarded as a falling edge that increments the frc. no. description timing chart low ? low: cks1 and cks0 are 1 rewritten while both clock sources are low. low ? high: cks1 and cks0 are 2 rewritten while old clock source is low and new clock source is high. high ? low: cks1 and cks0 are 3 rewritten while old clock source is high and new clock source is low. old clock source new clock source frc clock pulse frc cks rewrite n n + 1 old clock source new clock source frc clock pulse frc cks rewrite n n + 1 n + 2 old clock source new clock source frc clock pulse frc n n + 1 n + 2 cks rewrite * 150 table 6-4. effect of changing internal clock sources (cont.) no. description timing chart high ? high: cks1 and cks0 are 4 rewritten while both clock sources are high. old clock source new clock source frc clock pulse frc n n + 1 cks rewrite n + 2 151 section 7. 8-bit timers 7.1 overview the h8/330 chip includes an 8-bit timer module with two channels (tmr0 and tmr1). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare-match events. one application of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty factor. 7.1.1 features the features of the 8-bit timer module are listed below. selection of four clock sources the counters can be driven by an internal clock signal ( /8, /64, or /1024) or an external clock input (enabling use as an external event counter). selection of three ways to clear the counters the counters can be cleared on compare-match a or b, or by an external reset signal. timer output controlled by two time constants the timer output signal in each channel is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty factor. three independent interrupts compare-match a and b and overflow interrupts can be requested independently. 7.1.2 block diagram figure 7-1 shows a block diagram of one channel in the 8-bit timer module. the other channel is identical. 153 figure 7-1. block diagram of 8-bit timer 7.1.3 input and output pins table 7-1 lists the input and output pins of the 8-bit timer. table 7-1. input and output pins of 8-bit timer external clock source internal clock sources clock select comparator a tcora comparator b tcorb bus interface internal data bus tcsr tcr /8 /64 /1024 tmci compare- clear clock tmo overflow tmri match a compare- match b cmia cmib ovi control logic tcnt interrupt signals tcr: tcsr: tcora: tcorb: tcnt: timer control register (8 bits) timer control status register (8 bits) time constant register a (8 bits) time constant register b (8 bits) timer counter module data bus abbreviation name tmr0 tmr1 i/o function timer output tmo 0 tmo 1 output output controlled by compare-match timer clock input tmci 0 tmci 1 input external clock source for the counter timer reset input tmri 0 tmri 1 input external reset signal for the counter 154 7.1.4 register configuration table 7-2 lists the registers of the 8-bit timer module. each channel has an independent set of registers. table 7-2. 8-bit timer registers * software can write a ??to clear bits 7 to 5, but cannot write a ??in these bits. 7.2 register descriptions 7.2.1 timer counter (tcnt) ?h?fc8 (tmr0), h?fd0 (tmr1) each timer counter (tcnt) is an 8-bit up-counter that increments on a pulse generated from one of four clock sources. the clock source is selected by clock select bits 2 to 0 (cks2 to cks0) of the timer control register (tcr). the cpu can always read or write the timer counter. the timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. clock clear bits 1 and 0 (cclr1 and cclr0) of the timer control register select the method of clearing. when a timer counter overflows from h?f to h?0, the overflow flag (ovf) in the timer control/status register (tcsr) is set to ?. the timer counters are initialized to h?0 at a reset and in the standby modes. address name abbreviation r/w initial value tmr0 tmr1 timer control register tcr r/w h?0 h?fc8 h?fd0 timer control/status register tcsr r/(w)* h?0 h?fc9 h?fd1 timer constant register a tcora r/w h?f h?fca h?fd2 timer constant register b tcorb r/w h?f h?fcb h?fd3 timer counter tcnt r/w h?0 h?fcc h?fd4 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 155 7.2.2 time constant registers a and b (tcora and tcorb) ?h?fca and h?fcb (tmr0), h?fd2 and h?fd3 (tmr1) tcora and tcorb are 8-bit readable/writable registers. the timer count is continually compared with the constants written in these registers. when a match is detected, the corresponding compare-match flag (cmfa or cmfb) is set in the timer control/status register (tcsr). the timer output signal (tmo0 or tmo1) is controlled by these compare-match signals as specified by output select bits 3 to 0 (os3 to os0) in the timer control/status register (tcsr). tcora and tcorb are initialized to h?f at a reset and in the standby modes. compare-match is not detected during the t3 state of a write cycle to tcora or tcorb. see item (3) in section 7.6, "application notes." 7.2.3 timer control register (tcr) ?h?fc8 (tmr0), h?fd0 (tmr1) each tcr is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. the tcrs are initialized to h?0 at a reset and in the standby modes. bit 7 ?compare-match interrupt enable b (cmieb): this bit selects whether to request compare-match interrupt b (cmib) when compare-match flag b (cmfb) in the timer control/status register (tcsr) is set to ?. bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 156 bit 6 ?compare-match interrupt enable a (cmiea): this bit selects whether to request compare-match interrupt a (cmia) when compare-match flag a (cmfa) in the timer control/status register (tcsr) is set to ?. bit 5 ?timer overflow interrupt enable (ovie): this bit selects whether to request a timer overflow interrupt (ovi) when the overflow flag (ovf) in the timer control/status register (tcsr) is set to ?. bits 4 and 3 ?counter clear 1 and 0 (cclr1 and cclr0): these bits select how the timer counter is cleared: by compare-match a or b or by an external reset input. bits 2, 1, and 0 ?clock select (cks2, cks1, and cks0): these bits select the internal or external clock source for the timer counter. for the external clock source they select whether to increment the count on the rising or falling edge of the clock input, or on both edges. for the internal clock sources the count is incremented on the falling edge of the clock input. bit 7 cmieb description 0 compare-match interrupt request b (cmib) is disabled. (initial value) 1 compare-match interrupt request b (cmib) is enabled. bit 6 cmiea description 0 compare-match interrupt request a (cmia) is disabled. (initial value) 1 compare-match interrupt request a (cmia) is enabled. bit 5 ovie description 0 the timer overflow interrupt request (ovi) is disabled. (initial value) 1 the timer overflow interrupt request (ovi) is enabled. bit 4 bit 3 cclr1 cclr0 description 0 0 not cleared. (initial value) 0 1 cleared on compare-match a. 1 0 cleared on compare-match b. 1 1 cleared on rising edge of external reset input signal. 157 7.2.4 timer control/status register (tcsr) ?h?fc9 (tmr0), h?fd1 (tmr1) * software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. the tcsr is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. the tcsr is initialized to h?0 at a reset and in the standby modes. bit 7 ?compare-match flag b (cmfb): this status flag is set to ??when the timer count matches the time constant set in tcorb. cmfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6 ?compare-match flag a (cmfa): this status flag is set to ??when the timer count matches the time constant set in tcora. cmfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 no clock source (timer stopped) (initial value) 0 0 1 /8 internal clock source, counted on the falling edge 0 1 0 /64 internal clock source, counted on the falling edge 0 1 1 /1024 internal clock source, counted on the falling edge 1 0 0 no clock source (timer stopped) 1 0 1 external clock source, counted on the rising edge 1 1 0 external clock source, counted on the falling edge 1 1 1 external clock source, counted on both the rising and falling edges bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3 os2 os1 os0 initial value 0 0 0 1 0 0 0 0 read/write r/(w)* r/(w)* r/(w)* r/w r/w r/w r/w bit 7 cmfb description 0 to clear cmfb, the cpu must read cmfb after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when tcnt = tcorb. 158 bit 5 ?timer overflow flag (ovf): this status flag is set to ??when the timer count overflows (changes from h?f to h?0). ovf must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4 ?reserved: this bit is always read as ?.? it cannot be written. bits 3 to 0 ?output select 3 to 0 (os3 to os0): these bits specify the effect of compare-match events on the timer output signal (tcor or tcnt). bits os3 and os2 control the effect of compare-match b on the output level. bits os1 and os0 control the effect of compare-match a on the output level. if compare-match a and b occur simultaneously, any conflict is resolved as explained in item (4) in section 7.6, "application notes." after a reset, the timer output is "0" until the first compare-match event. when all four output select bits are cleared to ??the timer output signal is disabled. bit 6 cmfa description 0 to clear cmfa, the cpu must read cmfa after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when tcnt = tcora. bit 5 ovf description 0 to clear ovf, the cpu must read ovf after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when tcnt changes from h?f to h?0. bit 3 bit 2 os3 os2 description 0 0 no change when compare-match b occurs. (initial value) 0 1 output changes to ??when compare-match b occurs. 1 0 output changes to ??when compare-match b occurs. 1 1 output inverts (toggles) when compare-match b occurs. 159 7.3 operation 7.3.1 tcnt incrementation timing the timer counter increments on a pulse generated once for each period of the clock source selected by bits cks2 to cks0 of the tcr. internal clock: internal clock sources are created from the system clock by a prescaler. the counter increments on an internal tcnt clock pulse generated from the falling edge of the prescaler output, as shown in figure 7-2. bits cks2 to cks0 of the tcr can select one of the three internal clocks ( /8, /64, or /1024). figure 7-2. count timing for internal clock input external clock: if external clock input (tmci) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. figure 7-3 shows incrementation on both edges of the external clock signal. the external clock pulse width must be at least 1.5 system clock periods for incrementation on a single edge, and at least 2.5 system clock periods for incrementation on both edges. see figure 7.4. the counter will not increment correctly if the pulse width is shorter than these values. bit 1 bit 0 os1 os0 description 0 0 no change when compare-match a occurs. (initial value) 0 1 output changes to ??when compare-match a occurs. 1 0 output changes to ??when compare-match a occurs. 1 1 output inverts (toggles) when compare-match a occurs. n? n+1 n prescaler output tcnt clock pulse tcnt 160 figure 7-3. count timing for external clock input figure 7-4. minimum external clock pulse widths (example) 7.3.2 compare match timing (1) setting of compare-match flags a and b (cmfa and cmfb): the compare-match flags are set to ??by an internal compare-match signal generated when the timer count matches the time constant in tcnt or tcor. the compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. external clock source tcnt clock pulse tcnt n n + 1 n ?1 tmci tmci minimum tmci pulse width (single-edge incrementation) minimum tmci pulse width (double-edge incrementation) 161 accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. figure 7-5 shows the timing of the setting of the compare-match flags. figure 7-5. setting of compare-match flags (2) timing of compare-match flag (cmfa or cmfb) clearing: the compare-match flag cmfa or cmfb is cleared when the cpu writes a ??in this bit. figure 7-6. clearing of compare-match flags (3) output timing: when a compare-match event occurs, the timer output (tmo0 or tmo1) changes as specified by the output select bits (os3 to os0) in the tcsr. depending on these bits, the output can remain the same, change to ?,?change to ?,?or toggle. if compare-match a and b occur simultaneously, the higher priority compare-match determines the output level. see item (4) in section 7.6, ?pplication notes?for details. f tcnt tcor internal compare-match signal cmf n n + 1 n write cycle: cpu writes "0" in cmfa or cmfb t 1 t 2 t 3 cmfa or cmfb 162 figure 7-7 shows the timing when the output is set to toggle on compare-match a. figure 7-7. timing of timer output (4) timing of compare-match clear: depending on the cclr1 and cclr0 bits in the tcr, the timer counter can be cleared when compare-match a or b occurs. figure 7-8 shows the timing of this operation. figure 7-8. timing of compare-match clear 7.3.3 external reset of tcnt when the cclr1 and cclr0 bits in the tcr are both set to ?,?the timer counter is cleared on the rising edge of an external reset input. figure 7-9 shows the timing of this operation. the timer reset pulse width must be at least 1.5 system clock periods. internal compare-match a signal timer output (tmo) n h?0 internal compare-match signal tcnt 163 figure 7-9. timing of external reset 7.3.4 setting of tcsr overflow flag (1) setting of tcsr overflow flag (ovf): the overflow flag (ovf) is set to ??when the timer count overflows (changes from h?f to h?0). figure 7-10 shows the timing of this operation. figure 7-10. setting of overflow flag (ovf) (2) timing of tcsr overflow flag (ovf) clearing: the overflow flag (ovf) is cleared when the cpu writes a ??in this bit. external reset input (tmri) internal clear pulse tcnt n n ?1 h?0 h?0 tcnt internal overflow signal ovf h?f 164 figure 7-11. clearing of overflow flag 7.4 interrupts each channel in the 8-bit timer can generate three types of interrupts: compare-match a and b (cmia and cmib), and overflow (ovi). each interrupt is requested when the corresponding enable bits are set in the tcr and tcsr. independent signals are sent to the interrupt controller for each interrupt. table 7-3 lists information about these interrupts. table 7-3. 8-bit timer interrupts 7.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor. the control bits are set as follows: (1) in the tcr, cclr1 is cleared to ??and cclr0 is set to ??so that the timer counter is cleared when its value matches the constant in tcora. (2) in the tcsr, bits os3 to os0 are set to ?110,?causing the output to change to ??on compare-match a and to ??on compare-match b. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. when cycle: cpu writes "0" in ovf t 1 t 2 t 3 ovf interrupt description priority cmia requested when cmfa and cmiea are set high cmib requested when cmfb and cmieb are set ovi requested when ovf and ovie are set low 165 figure 7-12. example of pulse output 7.6 application notes application programmers should note that the following types of contention can occur in the 8-bit timer. (1) contention between tcnt write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. figure 7-13 shows this type of contention. figure 7-13. tcnt write-clear contention h?f tcora tcorb h?0 tmo pin clear counter tcnt internal address bus internal write signal counter clear signal tcnt n h?0 tcnt address write cycle: cpu writes to tcnt t 1 t 2 t 3 figure 7-13 166 (2) contention between tcnt write and increment: if a timer counter increment pulse is generated during the t 3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. figure 7-14 shows this type of contention. figure 7-14. tcnt write-increment contention (3) contention between tcor write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to tcora or tcorb, the write takes precedence and the compare- match signal is inhibited. figure 7-15 shows this type of contention. internal address bus internal write signal tcnt clock pulse tcnt n m tcnt address write cycle: cpu writes to tcnt t 1 write data t 2 t 3 figure 7-14 167 figure 7-15. contention between tcor write and compare-match (4) contention between compare-match a and compare-match b: if identical time constants are written in tcora and tcorb, causing compare-match a and b to occur simultaneously, any conflict between the output selections for compare-match a and b is resolved by following the priority order in table 7-4. table 7-4. priority of timer output (5) incrementation caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause the timer counter to increment. this depends on the time at which the clock select bits (cks2 to cks0) are rewritten, as shown in table 7-5. internal address bus internal write signal tcnt n m tcor address write cycle: cpu writes to tcora or tcorb n n + 1 tcora or tcorb compare-match a or b signal t 1 inhibited tcor write data figure 7-15 t 2 t 3 output selection priority toggle high ??output ??output no change low 168 the pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 7-5, the changeover generates a falling edge that triggers the tcnt clock pulse and increments the timer counter. switching between an internal and external clock source can also cause the timer counter to increment. this type of switching should be avoided at external clock edges. table 7-5. effect of changing internal clock sources * 1 including a transition from low to the stopped state (cks1 = 0, cks0 = 0), or a transition from the stopped state to low. * 2 including a transition from the stopped state to high. no. description timing chart low ? low* 1 : cks1 and cks0 are 1 rewritten while both clock sources are low. low ? high* 2 : cks1 and cks0 are 2 rewritten while old clock source is low and new clock source is high. n + 1 n old clock source new clock source tcnt clock pulse tcnt cks rewrite n + 1 n old clock source new clock source tcnt clock pulse tcnt cks rewrite n + 2 169 table 7-5. effect of changing internal clock sources (cont.) * 1 including a transition from high to the stopped state. * 2 the switching of clock sources is regarded as a falling edge that increments the tcnt. no. description timing chart high ? low* 1 : cks1 and cks0 are 3 rewritten while old clock source is high and new clock source is low. high ? high: cks1 and cks0 are 4 rewritten while both clock sources are high. old clock source new clock source tcnt clock pulse tcnt cks rewrite n n + 1 n + 2 * 3 * 2 n + 1 n old clock source new clock source tcnt clock pulse tcnt cks rewrite n + 2 170 section 8. pwm timers 8.1 overview the h8/330 has an on-chip pulse-width modulation (pwm) timer module with two independent channels (pwm0 and pwm1). both channels are functionally identical. each pwm channel generates a rectangular output pulse with a duty factor of 0 to 100%. the duty factor is specified in an 8-bit duty register (dtr). 8.1.1 features the pwm timer module has the following features: selection of eight clock sources duty factors from 0 to 100% with 1/250 resolution output with positive or negative logic and software enable/disable control 8.1.2 block diagram figure 8-1 shows a block diagram of one pwm timer channel. figure 8-1. block diagram of pwm timer comparator dtr bus interface internal data bus pulse tcr tcnt compare-match /2 /8 /32 /128 /256 /1024 /2048 /4096 output control clock clock select internal clock sources tcr: dtr: tcnt: timer control register (8 bits) duty register (8 bits) timer counter (8 bits) module data bus figure 8-1 171 8.1.3 input and output pins table 8-1 lists the output pins of the pwm timer module. there are no input pins. table 8-1. output pins of pwm timer module 8.1.4 register configuration the pwm timer module has three registers for each channel as listed in table 8-2. table 8-2. pwm timer registers * the timer counters are read/write registers, but the write function is for test purposes only. application programs should never write to these registers. 8.2 register descriptions 8.2.1 timer counter (tcnt) ?h?fa2 (pwm0), h?fa6 (pwm1) the pwm timer counters (tcnt) are 8-bit up-counters. when the output enable bit (oe) in the timer control register (tcr) is set to ?,?the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (cks2 to cks0). after counting from h?0 to h?9, the timer counter repeats from h?0. name abbreviation i/o function pwm0 output pw0 output pulse output from pwm timer channel 0. pwm1 output pw1 output pulse output from pwm timer channel 1. initial address name abbreviation r/w value pwm0 pwm1 timer control register tcr r/w h?8 h?fa0 h?fa4 duty register dtr r/w h?f h?fa1 h?fa5 timer counter tcnt r/(w)* h?0 h?fa2 h?fa6 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 172 the pwm timer counters can be read and written, but the write function is for test purposes only. application software should never write to a pwm timer counter, because this may have unpredictable effects. the pwm timer counters are initialized to h?0 at a reset and in the standby modes, and when the oe bit is cleared to ?. 8.2.2 duty register (dtr) ?h?fa1 (pwm0), h?fa5 (pwm1) the duty registers (dtr) are 8-bit readable/writable registers that specify the duty factor of the output pulse. any duty factor from 0 to 100% can be selected, with a resolution of 1/250. writing 0 (h?0) in a dtr gives a 0% duty factor; writing 125 (h?d) gives a 50% duty factor; writing 250 (h?a) gives a 100% duty factor. the timer count is continually compared with the dtr contents. if the dtr value is not 0, when the count increments from h?0 to h?1 the pwm output signal is set to ?.? when the count increments past the dtr value, the pwm output returns to ?.? if the dtr value is 0 (duty factor 0%), the pwm output remains constant at ?. the dtrs are double-buffered. a new value written in a dtr while the timer counter is running does not become valid until after the count changes from h?9 to h?0. when the timer counter is stopped (while the oe bit is ??, new values become valid as soon as written. when a dtr is read, the value read is the currently valid value. the dtrs are initialized to h?f at a reset and in the standby modes. 8.2.3 timer control register (tcr) ?h?fa0 (pwm0), h?fa4 (pwm1) bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w 173 the tcrs are 8-bit readable/writable registers that select the clock source and control the pwm outputs. the tcrs are initialized to h?8 at a reset and in the standby modes. bit 7 ?output enable (oe): this bit enables the timer counter and the pwm output. bit 6 ?output select (os): this bit selects positive or negative logic for the pwm output. bits 5 to 3 ?reserved: these bits cannot be modified and are always read as ?. bits 2, 1, and 0 ?clock select (cks2, cks1, and cks0): these bits select one of eight internal clock sources obtained by dividing the system clock ( ). from the clock source frequency, the resolution, period, and frequency of the pwm output can be calculated as follows. bit 7 oe description 0 pwm output is disabled. tcnt is cleared to h?0 and stopped. (initial value) 1 pwm output is enabled. tcnt runs. bit 6 os description 0 positive logic; positive-going pwm pulse, ??= high (initial value) 1 negative logic; negative-going pwm pulse, ??= low bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 /2 (initial value) 0 0 1 /8 0 1 0 /32 0 1 1 /128 1 0 0 /256 1 0 1 /1024 1 1 0 /2048 1 1 1 /4096 174 resolution = 1/clock source frequency pwm period = resolution 250 pwm frequency = 1/pwm period if the system clock frequency is 10mhz, then the resolution, period, and frequency of the pwm output for each clock source are given in table 8-3. table 8-3. pwm timer parameters for 10mhz system clock 8.3 operation 8.3.1 timer incrementation the pwm clock source is created from the system clock ( ) by a prescaler. the timer counter increments on a tcnt clock pulse generated from the falling edge of the prescaler output as shown in figure 8-2. figure 8-2. tcnt increment timing internal clock frequency resolution pwm period pwm frequency /2 200ns 50 s 20khz /8 800ns 200 s 5khz /32 3.2 s 800 s 1.25khz /128 12.8 s 3.2ms 312.5hz /256 25.6 s 6.4ms 156.3hz /1024 102.4 s 25.6ms 39.1hz /2048 204.8 s 51.2ms 19.5hz /4096 409.6 s 102.4ms 9.8hz tcnt clock pulse prescaler output tcnt n? n+1 n 175 8.3.2 pwm operation figure 8-3 is a timing chart of the pwm operation. n ?1 n + 1 (a) h?0 (b) h?1 h?2 n h?9 (d) h?0 h?1 n (d) m h?f (c) (a)* (e)* (b) (c) n written in dtr m written in dtr tcnt clock pulses oe tcnt dtr (os = ?? pwm output (os = ?? pwm 1 cycle * used for port 4 input/output: state depends on values in data register and data direction register. figure 8-3. pwm timing 176 (1) positive logic (os = ?? when (oe = ?? ?(a) in figure 8-3: the timer count is held at h?0 and pwm output is inhibited. (pin 46 (for pw0) or pin 47 (for pw1)is used for port 4 input/output, and its state depends on the corresponding port 4 data register and data direction register.) any value (such as n in figure 8-3) written in the dtr becomes valid immediately. - when (oe = ?? i) the timer counter begins incrementing. the pwm output goes high when tcnt changes from h?0 to h?1, unless dtr = h?0. [(b) in figure 8-3] ii) when the count passes the dtr value, the pwm output goes low. [(c) in figure 8-3] iii) if the dtr value is changed (by writing the data ??in figure 8-3), the new value becomes valid after the timer count changes from h?9 to h?0. [(d) in figure 8-3] (2) negative logic (os = ?? ?(e) in figure 8-3: the operation is the same except that high and low are reversed in the pwm output . [(e) in figure 8-3] 8.4 application notes some notes on the use of the pwm timer module are given below. (1) any necessary changes to the clock select bits (cks2 to cks0) and output select bit (os) should be made before the output enable bit (oe) is set to ?. (2) if the dtr value is h?0, the duty factor is 0% and pwm output remains constant at ?.? if the dtr value is h?a to h?f, the duty factor is 100% and pwm output remains constant at ?. (for positive logic, ??is low and ??is high. for negative logic, ??is high and ??is low.) (3) when the dtr is read, the currently valid value is obtained. due to the double buffering, this may not be the value most recently written. (4) software should never write to a pwm timer counter. the write function is for test purposes only and may have unintended effects in normal operation. 177 section 9. serial communication interface 9.1 overview the h8/330 chip includes a single-channel serial communication interface (sci) for transferring serial data to and from other chips. either the synchronous or asynchronous communication mode can be selected. communication control functions are provided by internal registers. 9.1.1 features the features of the on-chip serial communication interface are: separate pins for asynchronous and synchronous modes asynchronous mode the sci can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. eight data formats are available. data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even, odd, or none error detection: parity, overrun, and framing errors synchronous mode the sci can communicate with chips able to perform clocked serial data transfer. data length: 8 bits error detection: overrun errors full duplex communication the transmitting and receiving sections are independent, so the sci can transmit and receive simultaneously. both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. built-in baud rate generator any specified baud rate can be generated. internal or external clock source the baud rate generator can operate on an internal clock source, or an external clock signal input at the asck or csck pin. three interrupts transmit-end, receive-end, and receive-error interrupts are requested independently. 179 9.1.2 block diagram figure 9-1. block diagram of serial communication interface 9.1.3 input and output pins table 9-1 lists the input and output pins used by the sci module. table 9-1. sci input/output pins tdr bus interface internal data bus module data bus parity generate clock parity check tsr /4 /16 /64 arxd/ crxd atxd/ ctxd txi rxi eri interrupt signals external clock source internal clock rdr rsr asck/ csck brr communi- cation control ssr scr smr baud rate generator rsr: rdr: tsr: tdr: smr: scr: ssr: brr: receive shift register (8 bits) receive data register (8 bits) transmit shift register (8 bits) transmit data register (8 bits) serial mode register (8 bits) serial control register (8 bits) serial status register (8 bits) bit rate register (8 bits) name abbreviation i/o function asynchronous serial clock asck input/output serial clock input and output. asynchronous receive data arxd input receive data input. asynchronous transmit data atxd output transmit data output. synchronous serial clock csck input/output serial clock input and output. synchronous receive data crxd input receive data input. synchronous transmit data ctxd output transmit data output. 180 9.1.4 register configuration table 9-2 lists the sci registers. table 9-2. sci registers notes: * software can write a ??to clear the status flag bits, but cannot write a ?. 9.2 register descriptions 9.2.1 receive shift register (rsr) the rsr receives incoming data bits. when one data character (1 byte) has been received, it is transferred to the receive data register (rdr). the cpu cannot read or write the rsr directly. name abbreviation r/w initial value address receive shift register rsr receive data register rdr r h?0 h?fdd transmit shift register tsr transmit data register tdr r/w h?f h?fdb serial mode register smr r/w h?4 h?fd8 serial control register scr r/w h?c h?fda serial status register ssr r/(w)* h?7 h?fdc bit rate register brr r/w h?f h?fd9 bit 7 6 5 4 3 2 1 0 read/write 181 9.2.2 receive data register (rdr) ?h?fdd the rdr stores received data. as each character is received, it is transferred from the rsr to the rdr, enabling the rsr to receive the next character. this double-buffering allows the sci to receive data continuously. the cpu can read but not write the rdr. the rdr is initialized to h?0 at a reset and in the standby modes. 9.2.3 transmit shift register (tsr) the tsr holds the character currently being transmitted. when transmission of this character is completed, the next character is moved from the transmit data register (tdr) to the tsr and transmission of that character begins. if the cpu has not written the next character in the tdr, no data are transmitted. the cpu cannot read or write the tsr directly. 9.2.4 transmit data register (tdr) ?h?fdb the tdr is an 8-bit readable/writable register that holds the next character to be transmitted. when the tsr becomes empty, the character written in the tdr is transferred to the tsr. continuous data transmission is possible by writing the next byte in the tdr while the current byte is being transmitted from the tsr. bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r bit 7 6 5 4 3 2 1 0 read/write bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w 182 the tdr is initialized to h?f at a reset and in the standby modes. 9.2.5 serial mode register (smr) ?h?fd8 the smr is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. it is initialized to h?4 at a reset and in the standby modes. bit 7 ?communication mode (c/a): this bit selects the asynchronous or synchronous communication mode. bit 6 ?character length (chr): this bit selects the character length in asynchronous mode. it is ignored in synchronous mode. bit 5 ?parity enable (pe): this bit selects whether to add a parity bit in asynchronous mode. it is ignored in synchronous mode. bit 7 6 5 4 3 2 1 0 c/a chr pe o/e stop cks1 cks0 initial value 0 0 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w bit 7 c/a description 0 asynchronous communication. (initial value) 1 clock-synchronized communication. bit 6 chr description 0 8 bits per character. (initial value) 1 7 bits per character. bit 5 pe description 0 transmit: no parity bit is added. (initial value) receive: parity is not checked. 1 transmit: a parity bit is added. receive: parity is checked. 183 bit 4 ?parity mode (o/e ): in asynchronous mode, when parity is enabled (pe = ??, this bit selects even or odd parity. even parity means that a parity bit is added to the data bits for each character to make the total number of 1 s even. odd parity means that the total number of 1 s is made odd. this bit is ignored when pe = ?,?and in the synchronous mode. bit 3 ?stop bit length (stop): this bit selects the number of stop bits. it is ignored in the synchronous mode. bit 2 ?reserved: this bit cannot be modified and is always read as ?. bits 1 and 0 ?clock select 1 and 0 (cks1 and cks0): these bits select the internal clock source when the baud rate generator is clocked from within the h8/330 chip. for further information about smr settings, see tables 9-5 to 9-7 in section 9.3, "operation." bit 4 o/e description 0 even parity. (initial value) 1 odd parity. bit 3 stop description 0 1 stop bit. (initial value) 1 2 stop bits. bit 1 bit 0 cks1 cks0 description 0 0 clock (initial value) 0 1 /4 clock 1 0 /16 clock 1 1 /64 clock 184 9.2.6 serial control register (scr) ?h?fda the scr is an 8-bit readable/writable register that enables or disables various sci functions. it is initialized to h?c at a reset and in the standby modes. bit 7 ?transmit interrupt enable (tie): this bit enables or disables the transmit-end interrupt (txi) requested when the transmit data register empty (tdre) bit in the serial status register (ssr) is set to ?. bit 6 ?receive interrupt enable (rie): this bit enables or disables the receive-end interrupt (rxi) requested when the receive data register full (rdrf) bit in the serial status register (ssr) is set to ?. bit 5 ?transmit enable (te): this bit enables or disables the transmit function. when the transmit function is enabled, the atxd or ctxd pin is automatically used for output. when the transmit function is disabled, the atxd or ctxd pin can be used as a general-purpose i/o port. bit 7 6 5 4 3 2 1 0 tie rie te re cke1 cke0 initial value 0 0 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w bit 7 tie description 0 the transmit-end interrupt request (txi) is disabled. (initial value) 1 the transmit-end interrupt request (txi) is enabled. bit 6 rie description 0 the receive-end interrupt (rxi) request is disabled. (initial value) 1 the receive-end interrupt (rxi) request is enabled. bit 5 te description 0 the transmit function is disabled. (initial value) the atxd and ctxd pins can be used for general-purpose i/o. 1 the transmit function is enabled. when c/a = 0, the atxd pin is used for output. when c/a = 1, the ctxd pin is used for output. 185 bit 4 ?receive enable (re): this bit enables or disables the receive function. when the receive function is enabled, the arxd or crxd pin is automatically used for input. when the receive function is disabled, the arxd or crxd pin is available as a general-purpose i/o port. bits 3 and 2 ?reserved: these bits cannot be modified and are always read as ?. bit 1 ?clock enable 1 (cke1): this bit selects the internal or external clock source for the baud rate generator. when the external clock source is selected, the asck or csck pin is automatically used for input of the external clock signal. bit 0 ?clock enable 0 (cke0): when an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the asck pin. this bit is ignored when the external clock is selected, or when the synchronous mode is selected. for further information on clock source selection, see table 9-6 in section 9.3, ?peration. bit 4 re description 0 the receive function is disabled. the arxd and crxd pins can be (initial value) used for general-purpose i/o. 1 the receive function is enabled. when c/a = 0, the arxd pin is used for input. when c/a = 1, the crxd pin is used for input. bit 1 cke1 description 0 internal clock source. (when c/a = 1, the csck pin is used (initial value) for output.) 1 external clock source. (when c/a = 1, the csck pin is used for input. when c/a = 0, the asck pin is used for input.) bit 0 cke0 description 0 the asck pin is not used by the sci (and is available as (initial value) a general-purpose i/o port). 1 the asck pin is used for serial clock output. 186 9.2.7 serial status register (ssr) ?h?fdc * software can write a ??to clear the flags, but cannot write a ??in these bits. the ssr is an 8-bit register that indicates transmit and receive status. it is initialized to h?7 at a reset and in the standby modes. bit 7 ?transmit data register empty (tdre): this bit indicates when the tdr contents have been transferred to the tsr and the next character can safely be written in the tdr. bit 6 ?receive data register full (rdrf): this bit indicates when one character has been received and transferred to the rdr. bit 7 6 5 4 3 2 1 0 tdre rdrf orer fer per initial value 1 0 0 0 0 1 1 1 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* bit 7 tdre description 0 to clear tdre, the cpu must read tdre after it has been set to "1," then write a ? in this bit. 1 this bit is set to 1 at the following times: (initial value) (1) when tdr contents are transferred to the tsr. (2) when the te bit in the scr is cleared to "0." bit 6 rdrf description 0 to clear rdrf, the cpu must read rdrf after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when one character is received without error and transferred from the rsr to the rdr. 187 bit 5 ?overrun error (orer): this bit indicates an overrun error during reception. bit 4 ?framing error (fer): this bit indicates a framing error during data reception in the asynchronous mode. it has no meaning in the synchronous mode. bit 3 ?parity error (per): this bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. this bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. bits 2 to 0 ?reserved: these bits cannot be modified and are always read as ?. bit 5 orer description 0 to clear orer, the cpu must read orer after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 if reception of the next character ends while the receive data register is still full (rdrf = ??. bit 4 fer description 0 to clear fer, the cpu must read fer after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 if a framing error occurs (stop bit = ??. bit 3 per description 0 to clear per, the cpu must read per after (initial value) it has been set to "1," then write a ??in this bit. 1 this bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the o/e bit in the smr). 188 9.2.8 bit rate register (brr) ?h?fd9 the brr is an 8-bit register that, together with the cks1 and cks0 bits in the smr, determines the baud rate output by the baud rate generator. the brr is initialized to h?f (the slowest rate) at a reset and in the standby modes. tables 9-3 and 9-4 show examples of brr (n) and cks (n) settings for commonly used bit rates. table 9-3. examples of brr settings in asynchronous mode (1) bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w xtal frequency (mhz) 2 2.4576 4 4.194304 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 ?.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 ?.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 0 7 0 0 12 +0.16 0 13 ?.48 9600 0 3 0 19200 0 1 0 31250 0 1 0 38400 0 0 0 189 table 9-3. examples of brr settings in asynchronous mode (2) table 9-3. examples of brr settings in asynchronous mode (3) xtal frequency (mhz) 4.9152 6 7.3728 8 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 1 174 ?.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 ?.34 0 23 0 0 25 +0.16 9600 0 7 0 0 11 0 0 12 +0.16 19200 0 3 0 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 xtal frequency (mhz) 9.8304 10 12 12.288 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 2 86 +0.31 2 88 ?.25 2 106 ?.44 2 108 +0.08 150 1 255 0 2 64 +0.16 2 77 0 2 79 0 300 1 127 0 1 129 +0.16 1 155 0 1 159 0 600 0 255 0 1 64 +0.16 1 77 0 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 ?.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 ?.34 0 19 0 19200 0 7 0 0 7 +1.73 0 4 0 31250 0 4 ?.70 0 4 0 0 5 0 0 5 +2.40 38400 0 3 0 0 3 +1.73 190 table 9-3. examples of brr settings in asynchronous mode (4) note: if possible, the error should be within 1%. b = osc 10 6 /[64 2 2n (n + 1)] n : brr value (0 n 255) osc : crystal oscillator frequency in mhz b : bit rate (bits/second) n : internal clock source (0, 1, 2, or 3) the meaning of n is given by the table below: xtal frequency (mhz) 14.7456 16 19.6608 20 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 2 130 ?.07 2 141 +0.03 2 174 ?.26 3 43 +0.88 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 ?.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 0 7 0 0 9 ?.70 0 9 0 38400 0 5 0 0 7 0 0 7 +1.73 n cks1 cks0 clock 0 0 0 1 0 1 /4 2 1 0 /16 3 1 1 /64 191 table 9-4. examples of brr settings in synchronous mode notes: blank: no setting is available. ? a setting is available, but the bit rate is inaccurate. *: continuous transfer is not possible. b = osc 10 6 /[8 2 2n (n + 1)] n : brr value (0 n 255) osc : crystal oscillator frequency in mhz b : bit rate (bits per second) n : internal clock source (0, 1, 2, or 3) the meaning of n is given by the table below: xtal frequency (mhz) bit 2 4 8 10 16 20 rate n n n n n n n n n n n n 100 250 1 249 2 124 2 249 3 124 500 1 124 1 249 2 124 2 249 1k 0 249 1 124 1 249 2 124 2.5k 0 99 0 199 1 99 1 124 1 199 1 249 5k 0 49 0 99 0 199 0 249 1 99 1 124 10k 0 24 0 49 0 99 0 124 0 199 0 249 25k 0 9 0 19 0 39 0 49 0 79 0 99 50k 0 4 0 9 0 19 0 24 0 39 0 49 100k 0 4 0 9 0 19 0 24 250k 0 0* 0 1 0 3 0 4 0 7 0 9 500k 0 0* 0 1 0 3 0 4 1m 0 0* 0 1 2.5m 0 0* n cks1 cks0 clock 0 0 0 1 0 1 /4 2 1 0 /16 3 1 1 /64 192 9.3 operation 9.3.1 overview the sci supports serial data transfer in both asynchronous and synchronous modes. the communication format depends on settings in the smr as indicated in table 9-5. the clock source and usage of the asck and csck pins depend on settings in the smr and scr as indicated in table 9-6. table 9-5. communication formats used by sci table 9-6. sci clock source selection * not used by the sci. smr stop bit c/a chr pe stop mode format parity length 0 0 0 0 none 1 1 8-bit data 2 1 0 yes 1 1 asynchronous 2 1 0 0 none 1 1 7-bit data 2 1 0 yes 1 1 2 1 synchronous 8-bit data smr scr clock c/a cke1 cke0 source asck pin csck pin 0 0 0 internal input/output port* input/output port* (async 1 serial clock output input/output port* mode) at bit rate 1 0 external serial clock input input/output port* 1 at 16 bit rate 1 0 0 internal input/output port* serial clock output (sync 1 mode) 1 0 external input/output port* serial clock input 1 193 transmitting and receiving operations in the two modes are described next. 9.3.2 asynchronous mode in asynchronous mode, each character is individually synchronized by framing it with a start bit and stop bit. full duplex data transfer is possible because the sci has independent transmit and receive sections. double buffering in both sections enables the sci to be programmed for continuous data transfer. figure 9-2 shows the general format of one character sent or received in the asynchronous mode. the communication channel is normally held in the mark state (high). character transmission or reception starts with a transition to the space state (low). the first bit transmitted or received is the start bit (low). it is followed by the data bits, in which the least significant bit (lsb) comes first. the data bits are followed by the parity bit, if present, then the stop bit or bits (high) confirming the end of the frame. in receiving, the sci synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). figure 9-2. data format in asynchronous mode (1) data format: table 9-7 lists the data formats that can be sent and received in asynchronous mode. eight formats can be selected by bits in the smr. d0 d1 dn start bit 1 bit 7 or 8 bits one character parity bit stop bit 0 or 1 bit 1 or 2 bits idle state 194 table 9-7. data formats in asynchronous mode note start: start bit stop: stop bit p: parity bit (2) clock: in the asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the asck pin. refer to table 9-6. if an external clock is input at the asck pin, its frequency should be 16 times the desired baud rate. if the internal clock provided by the on-chip baud rate generator is selected and the asck pin is used for clock output, the output clock frequency is equal to the baud rate, and the clock pulse rises at the center of the transmit data bits. figure 9-3 shows the phase relationship between the output clock and transmit data. figure 9-3. phase relationship between clock output and transmit data smr bits chr pe stop data format 0 0 0 start 8-bit data stop 0 0 1 start 8-bit data stop stop 0 1 0 start 8-bit data p stop 0 1 1 start 8-bit data p stop stop 1 0 0 start 7-bit data stop 1 0 1 start 7-bit data stop stop 1 1 0 start 7-bit data p stop 1 1 1 start 7-bit data p stop stop ...... output clock transmit data start bit d1 d2 d3 . . . . . . . . . . . . 195 (3) data transmission and reception sci initialization: before data can be transmitted or received, the sci must be initialized by software. to initialize the sci, software must clear the te and re bits to ?,?then execute the following procedure. write the value corresponding to the desired bit rate in the brr. (this step is not necessary if an external clock is used.) select the desired communication parameters in the scr. leave bit 0 (cke0) cleared to zero. select clocked synchronous mode in the smr. set the te and/or re bit in the scr to ?. the te and re bits must both be cleared to ??whenever the operating mode or data format is changed. after changing the operating mode or data format, before setting the te and re bits to ? software must wait for at least the transfer time for 1 bit at the selected baud rate, to make sure the sci is initialized. if an external clock is used, the clock must not be stopped. when clearing the tdre bit during data transmission, to assure transfer of the correct data, do not clear the tdre bit until after writing data in the tdr. similarly, in receiving data, do not clear the rdrf bit until after reading data from the rdr. data transmission: the procedure for transmitting data is as follows. set up the desired transmitting conditions in the smr, scr, and brr. set the te bit in the scr to ?. the atxd pin will automatically be switched to output and one frame* of all 1 s will be transmitted, after which the sci is ready to transmit data. check that the tdre bit is set to ?,?then write the first byte of transmit data in the tdr. next clear the tdre bit to ?. 196 ? the first byte of transmit data is transferred from the tdr to the tsr and sent in the designated format as follows. i) start bit (one ??bit). ii) transmit data (seven or eight bits, starting from bit 0) iii) parity bit (odd or even parity bit, or no parity bit) iv) stop bit (one or two consecutive ??bits) transfer of the transmit data from the tdr to the tsr makes the tdr empty, so the tdre bit is set to ?. if the tie bit is set to ?,?a transmit-end interrupt (txi) is requested. when the transmit function is enabled but the tdr is empty (tdre = ??, the output at the atxd pin is held at ??until the tdre bit is cleared to ?. * a frame is the data for one character, including the start bit and stop bit(s). data reception: the procedure for receiving data is as follows. set up the desired receiving conditions in the smr, scr, and brr. set the re bit in the scr to ?. the arxd pin is automatically be switched to input and the sci is ready to receive data. the sci synchronizes with the incoming data by detecting the start bit, and places the received bits in the rsr. at the end of the data, the sci checks that the stop bit is ?. when a complete frame has been received, the sci transfers the received data from the rsr to the rdr so that it can be read. if the character length is 7 bits, the most significant bit of the rdr is cleared to ?. at the same time, the sci sets the rdrf bit in the ssr to ?.? if the rie bit is set to ?,?a receive-end interrupt (rxi) is requested. the rdrf bit is cleared to ??when software reads the ssr, then writes a ??in the rdrf bit. the rdr is then ready to receive the next character from the rsr. when a frame is not received correctly, a receive error occurs. there are three types of receive errors, listed in table 9-8. 197 if a receive error occurs, the rdrf bit in the ssr is not set to ?.? (for an overrun error, rdrf is already set to "1.") the corresponding error flag is set to ??instead. if the rie bit in the scr is set to ?,?a receive-error interrupt (eri) is requested. when a framing or parity error occurs, the rsr contents are transferred to the rdr. if an overrun error occurs, however, the rsr contents are not transferred to the rdr. if multiple receive errors occur simultaneously, all the corresponding error flags are set to ?. to clear a receive-error flag (orer, fer, or per), software must read the ssr and then write a ??in the flag bit. table 9-8. receive errors 9.3.3 synchronous mode the synchronous mode is suited for high-speed, continuous data transfer. each bit of data is synchronized with a serial clock pulse at the csck pin. continuous data transfer is enabled by the double buffering employed in both the transmit and receive sections of the sci. full duplex communication is possible because the transmit and receive sections are independent. (1) data format: figure 9-4 shows the communication format used in the synchronous mode. the data length is 8 bits for both the transmit and receive directions. the least significant bit (lsb) is sent and received first. each bit of transmit data is output from the falling edge of the serial clock pulse to the next falling edge. received bits are latched on the rising edge of the serial clock pulse. name abbreviation description overrun error orer reception of the next frame ends while the rdrf bit is still set to ?. the rsr contents are not transferred to the rdr. framing error fer a stop bit is ?.? the rsr contents are transferred to the rdr. parity error per the parity of a frame does not match the value selected by the o/e bit in the smr. the rsr contents are transferred to the rdr. 198 figure 9-4. data format in synchronous mode (2) clock: either the internal serial clock created by the on-chip baud rate generator or an external clock input at the csck pin can be selected in the synchronous mode. see table 9-6 for details. (3) data transmission and reception sci initialization: before data can be transmitted or received, the sci must be initialized by software. to initialize the sci, software must clear the te and re bits to ??to disable both the transmit and receive functions, then execute the following procedure. write the value corresponding to the desired bit rate in the brr. (this step is not necessary if an external clock is used.) select the clock and enable desired interrupts in the scr. leave bit 0 (cke0) cleared to "0." select the synchronous mode in the smr. set the te and/or re bit in the scr to ?. the te and re bits must both be cleared to ??whenever the operating mode or data format is changed. after changing the operating mode or data format, before setting the te and re bits to ??software must wait for at least 1 bit transfer time at the selected communication speed, to make sure the sci is initialized. don?-care don?-care data serial clock bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 transmission direction serial clock data 8-bit data 8-bit data 199 when clearing the tdre bit during data transmission, to assure correct data transfer, do not clear the tdre bit until after writing data in the tdr. similarly, in receiving data, do not clear the rdrf bit until after reading data from the rdr. data transmission: the procedure for transmitting data is as follows. set up the desired transmitting conditions in the smr, brr, and scr. set the te bit in the scr to ?. the ctxd pin will automatically be switched to output, after which the sci is ready to transmit data. check that the tdre bit is set to ?,?then write the first byte of transmit data in the tdr. next clear the tdre bit to ?. the first byte of transmit data is transferred from the tdr to the tsr and sent, each bit synchronized with a clock pulse. bit 0 is sent first. transfer of the transmit data from the tdr to the tsr makes the tdr empty, so the tdre bit is set to ?.? if the tie bit is set to ?,?a transmit-end interrupt (txi) is requested. the tdr and tsr function as a double buffer. continuous data transmission can be achieved by writing the next transmit data in the tdr and clearing the tdre bit to ??while the sci is transmitting the current data from the tsr. if an internal clock source is selected, after transferring the transmit data from the tdr to the tsr, while transmitting the data from the tsr the sci also outputs a serial clock signal at the csck pin. when all data bits in the tsr have been transmitted, if the tdr is empty (tdre = ??, serial clock output is suspended until the next data byte is written in the tdr and the tdre bit is cleared to ?.? during this interval the ctxd pin continues to output the value of the last bit of the previous data. if the external clock source is selected, data transmission is synchronized with the clock signal input at the csck pin. when all data bits in the tsr have been transmitted, if the tdr is empty (tdre = ?? but external clock pulses continue to arrive, the ctxd pin outputs the value of last bit of the previous data. data reception: the procedure for receiving data is as follows. 200 set up the desired receiving conditions in the smr, brr, and scr. set the re bit in the scr to ?. the crxd pin is automatically be switched to input and the sci is ready to receive data. incoming data bits are latched in the rsr on eight clock pulses. when 8 bits of data have been received, the sci sets the rdrf bit in the ssr to ?.? if the rie bit is set to ?,?a receive-end interrupt (rxi) is requested. the sci transfers the received data byte from the rsr to the rdr so that it can be read. the rdrf bit is cleared when software reads the rdrf bit in the ssr, then writes a ??in the rdrf bit. the rdr and rsr function as a double buffer. data can be received continuously by reading each byte of data from the rdr and clearing the rdrf bit to ??before the last bit of the next byte is received. in general, an external clock source should be used for receiving data. if an internal clock source is selected, the sci starts receiving data as soon as the re bit is set to ?.? the serial clock is also output at the csck pin. the sci continues receiving until the re bit is cleared to ?. if the last bit of the next data byte is received while the rdrf bit is still set to ?,?an overrun error occurs and the orer bit is set to ?.? if the rie bit is set to ?,?a receive-error interrupt (eri) is requested. the data received in the rsr are not transferred to the rdr when an overrun error occurs. after an overrun error, reception of the next data is enabled when the orer bit is cleared to ?. simultaneous transmit and receive: the procedure for transmitting and receiving simultaneously is as follows: set up the desired communication conditions in the smr, brr, and scr. set the te and re bits in the scr to ?. the ctxd and crxd pins are automatically switched to output and input, respectively, and the sci is ready to transmit and receive data. 201 a data transmitting and receiving start when the tdre bit in the ssr is cleared to ?. data are sent and received in synchronization with eight clock pulses. first, the transmit data are transferred from the tdr to the tsr. this makes the tdr empty, so the tdre bit is set to ?.? if the tie bit is set to ?,?a transmit-end interrupt (txi) is requested. if continuous data transmission is desired, software must read the tdre bit in the ssr, write the next transmit data in the tdr, then clear the tdre bit to ?. if the tdre bit is not cleared to ??by the time the sci finishes sending the current byte from the tsr, the ctxd pin continues to output the value of last bit of the previous data. in the receiving section, when 8 bits of data have been received they are transferred from the rsr to the rdr and the rdrf bit in the ssr is set to ?.? if the rie bit is set to ?,?a receive-end interrupt (rxi) is requested. to clear the rdrf bit software should read the rdrf bit in the ssr, read the data in the rdr, then write a ??in the rdrf bit. for continuous data reception, software should read the rdrf bit in the ssr, read the data in the rdr, then clear the rdrf bit to ?.? if the last bit of the next byte is received while the rdrf bit is still set to ?,?an overrun error occurs. the error is handled as described under ?ata reception?above. the overrun error does not affect the transmit section of the sci, which continues to transmit normally. 9.4 interrupts the sci can request three types of interrupts: transmit-end (txi), receive-end (rxi), and receive- error (eri). interrupt requests are enabled or disabled by the tie and rie bits in the scr. independent signals are sent to the interrupt controller for each type of interrupt. the transmit-end and receive-end interrupt request signals are obtained from the tdre and rdrf flags. the receive-error interrupt request signal is the logical or of the three error flags: overrun error (orer), framing error (fer), and parity error (per). table 9-9 lists information about these interrupts. 202 table 9-9. sci interrupts figure 9-5 shows the timing of the rxi interrupt signal. the timing of txi and eri is similar. figure 9-5. timing of interrupt signal 9.5 application notes application programmers should note the following features of the sci. (1) tdr write: the tdre bit in the ssr is simply a flag that indicates that the tdr contents have been transferred to the tsr. the tdr contents can be rewritten regardless of the tdre value. if a new byte is written in the tdr while the tdre bit is ?,?before the old tdr contents have been moved into the tsr, the old byte will be lost. normally, software should check that the tdre bit is set to ??before writing to the tdr. (2) multiple receive errors: table 9-10 lists the values of flag bits in the ssr when multiple receive errors occur, and indicates whether the rsr contents are transferred to the rdr. interrupt description priority eri receive-error interrupt, requested when orer, fer, or per high is set. rie must also be set. rxi receive-end interrupt, requested when rdrf and rie are set. txi transmit-end interrupt, requested when tdre and tie are set. low internal receive- end signal rdrf rxi figure 9-5 203 table 9-10. ssr bit states and data transfer when multiple receive errors occur * 1 set to ??before the overrun error occurs. * 2 yes: the rsr contents are transferred to the rdr. no: the rsr contents are not transferred to the rdr. (3) line break detection: when the arxd pin receives a continuous stream of 0 s in the asynchronous mode (line-break state), a framing error occurs because the sci detects a ??stop bit. the value h?0 is transferred from the rsr to the rdr. software can detect the line-break state as a framing error accompanied by h?0 data in the rdr. the sci continues to receive data, so if the fer bit is cleared to ??another framing error will occur. (4) sampling timing and receive margin in asynchronous mode: the serial clock used by the sci in asynchronous mode runs at 16 times the baud rate. the falling edge of the start bit is detected by sampling the arxd input on the falling edge of this clock. after the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. see figure 9-6. it follows that the receive margin can be calculated as in equation (1). when the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). this is a theoretical limit, however. in practice, system designers should allow a margin of 20% to 30%. ssr bits receive error rdrf orer fer per rsr ? rdr* 2 overrun error 1* 1 1 0 0 no framing error 0 0 1 0 yes parity error 0 0 0 1 yes overrun + framing errors 1* 1 1 1 0 no overrun + parity errors 1* 1 1 0 1 no framing + parity errors 0 0 1 1 yes overrun + framing + parity errors 1* 1 1 1 1 no 204 figure 9-6. sampling timing (asynchronous mode) m = {(0.5 ?1/2n) ?(d ?0.5)/n ?(l ?0.5)f} 100 [%] (1) m : receive margin n : ratio of basic clock to baud rate (n=16) d : duty factor of clock?atio of high pulse width to low width (0.5 to 1.0) l : frame length (9 to 12) f : absolute clock frequency deviation when d = 0.5 and f= 0 m = (0.5 ?/2 16) 100 [%] = 46.875% (2) 1 2 4 0 5 6 7 8 9 3 2 1 2 3 4 5 6 7 8 9 1 1 1 1 2 1 3 1 4 1 5 1 6 1 0 1 3 1 4 1 5 1 6 1 2 1 0 1 1 3 4 5 basic clock sync sampling data sampling d0 d1 receive data start bit ?.5 pulses +7.5 pulses 205 section 10. a/d converter 10.1 overview the h8/330 chip includes an analog-to-digital converter module with eight input channels. a/d conversion is performed by the successive approximations method with 8-bit resolution. 10.1.1 features the features of the on-chip a/d module are: eight analog input channels 8-bit resolution rapid conversion conversion time is 12.2 s per channel (minimum) with a 10mhz system clock external triggering can be selected single and scan modes single mode: a/d conversion is performed once. scan mode: a/d conversion is performed in a repeated cycle on one to four channels. four 8-bit data registers these registers store a/d conversion results for up to four channels. a cpu interrupt (adi) can be requested at the completion of each a/d conversion cycle. 207 10.1.2 block diagram figure 10-1. block diagram of a/d converter module data bus internal data bus successive approximations register a d d r a a d d r b a d d r c a d d r d a d c s r a d c r analog multi- plexer + comparator sample and hold circuit interrupt signal /8 /16 bus interface adtrg adi 8 bit d/a control circuit an 0 an 2 an 1 an 3 an 4 an 5 an 6 an 7 av cc av ss adcr: a/d control register (8 bits) adcsr: a/d control/status register (8 bits) addra: a/d data register a (8 bits) addrb: a/d data register b (8 bits) addrc: a/d data register c (8 bits) addrd: a/d data register d (8 bits) 208 10.1.3 input pins table 10-1 lists the input pins used by the a/d converter module. the eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (an 0 to an 3 ) and analog inputs 4 to 7 (an 4 to an 7 ), respectively. table 10-1. a/d input pins 10.1.4 register configuration table 10-2 lists the registers of the a/d converter module. table 10-2. a/d registers * software can write a "0" to clear bit 7, but cannot write a "1" in this bit. name abbreviation i/o function analog supply voltage av cc input power supply and reference voltage for the analog circuits. analog ground av ss input ground and reference voltage for the analog circuits. analog input 0 an 0 input analog input 1 an 1 input analog input pins, group 0 analog input 2 an 2 input analog input 3 an 3 input analog input 4 an 4 input analog input 5 an 5 input analog input pins, group 1 analog input 6 an 6 input analog input 7 an 7 input a/d external trigger adtrg input external trigger for starting a/d conversion name abbreviation r/w initial value address a/d data register a addra r h?0 h?fe0 a/d data register b addrb r h?0 h?fe2 a/d data register c addrc r h?0 h?fe4 a/d data register d addrd r h?0 h?fe6 a/d control/status register adcsr r/(w)* h?0 h?fe8 a/d control register adcr r/w h?f h?fea 209 10.2 register descriptions 10.2.1 a/d data registers (addr) ?h?fe0 to h'ffe6 the four a/d data registers (addra to addrd) are 8-bit read-only registers that store the results of a/d conversion. each data register is assigned to two analog input channels as indicated in table 10-3. the a/d data registers are always readable by the cpu. the a/d data registers are initialized to h?0 at a reset and in the standby modes. table 10-3. assignment of data registers to analog input channels 10.2.2 a/d control/status register (adcsr) ?h?fe8 * software can write a ??in bit 7 to clear the flag, but cannot write a ??in this bit. the a/d control/status register (adcsr) is an 8-bit readable/writable register that controls the operation of the a/d converter module. bit 7 6 5 4 3 2 1 0 addrn initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r (n = a to d) analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd bit 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/w r/w r/w r/w r/w r/w r/w 210 the adcsr is initialized to h?0 at a reset and in the standby modes. bit 7 ?a/d end flag (adf): this status flag indicates the end of one cycle of a/d conversion. bit 6 ?a/d interrupt enable (adie): this bit selects whether to request an a/d interrupt (adi) when a/d conversion is completed. bit 5 ?a/d start (adst): the a/d converter operates while this bit is set to ?.? in the single mode, this bit is automatically cleared to ??at the end of each a/d conversion. bit 7 adf description 0 to clear adf, the cpu must read adf after (initial value) it has been set to "1," then write a "0" in this bit. 1 this bit is set to 1 at the following times: (1) single mode: when one a/d conversion is completed. (2) scan mode: when inputs on all selected channels have been converted. bit 6 adie description 0 the a/d interrupt request (adi) is disabled. (initial value) 1 the a/d interrupt request (adi) is enabled. bit 5 adst description 0 a/d conversion is halted. (initial value) 1 (1) single mode: one a/d conversion is performed. the adst bit is automatically cleared to ??at the end of the conversion. (2) scan mode: a/d conversion starts and continues cyclically on the selected channels until the adst bit is cleared to ??by software (or a reset, or by entry to a standby mode). 211 bit 4 ?scan mode (scan): this bit selects the scan mode or single mode of operation. see section 10.3, ?peration?for descriptions of these modes. the mode should be changed only when the adst bit is cleared to ?. bit 3 ?clock select (cks): this bit controls the a/d conversion time. the conversion time should be changed only when the adst bit is cleared to ?. bits 2 to 0 ?channel select 2 to 0 (ch2 to ch0): these bits and the scan bit combine to select one or more analog input channels. the channel selection should be changed only when the adst bit is cleared to ?. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3 cks description 0 conversion time = 242 states (max.) (initial value) 1 conversion time = 122 states (max.) group select channel select selected channels ch2 ch1 ch0 single mode scan mode 0 0 0 an 0 (initial value) an 0 0 1 an 1 an 0 , an 1 1 0 an 2 an 0 to an 2 1 1 an 3 an 0 to an 3 1 0 0 an 4 an 4 0 1 an 5 an 4 , an 5 1 0 an 6 an 4 to an 6 1 1 an 7 an 4 to an 7 212 10.2.3 a/d control register (adcr) ?h?fea the a/d control register (adcr) is an 8-bit readable/writable register that enables or disables the a/d external trigger signal. the adcr is initialized to h?f at a reset and in the standby modes. bit 7 ?trigger enable (trge): this bit enables the adtrg (a/d external trigger) signal to set the adst bit and start a/d conversion. bits 6 to 0 ?reserved: these bits cannot be modified and are always read as ?. 10.3 operation the a/d converter performs 8 successive approximations to obtain a result ranging from h?0 (corresponding to av ss ) to h?f (corresponding to av cc ). figure 10-2 shows the response of the a/d converter. bit 7 6 5 4 3 2 1 0 trge initial value 0 1 1 1 1 1 1 1 read/write r/w bit 7 trge description 0 a/d external trigger is disabled. adtrg does not set (initial value) the adst bit. 1 a/d external trigger is enabled. adtrg sets the adst bit. (the adst bit can also be set by software.) 213 figure 10-2. the response of the a/d converter the a/d converter module can be programmed to operate in single mode or scan mode as explained below. 10.3.1 single mode (scan = 0) the single mode is suitable for obtaining a single data value from a single channel. a/d conversion starts when the adst bit is set to ?,?either by software or by a high-to-low transition of the adtrg signal (if enabled). during the conversion process the adst bit remains set to ?.? when conversion is completed, the adst bit is automatically cleared to ?. when the conversion is completed, the adf bit is set to ?.? if the interrupt enable bit (adie) is also set to ?,?an a/d conversion end interrupt (adi) is requested, so that the converted data can be processed by an interrupt-handling routine. the adf bit is cleared when software reads the a/d control/status register (adcsr), then writes a ??in this bit. before selecting the single mode, clock, and analog input channel, software should clear the adst bit to ??to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. a/d conversion begins when the adst bit is set to "1" again. the same instruction can be used to alter the mode and channel selection and set adst to "1." h'ff h'00 avss avcc 214 the following example explains the a/d conversion process in single mode when channel 1 (an1) is selected and the external trigger is disabled. figure 10-3 shows the corresponding timing chart. (1) software clears the adst bit to ?,?then selects the single mode (scan = ?? and channel 1 (ch2 to ch0 = ?01?, enables the a/d interrupt request (adie = ??, and sets the adst bit to ??to start a/d conversion. coding example: (when using the slow clock, cks = ?? bclr #5, @h?fe8 ; clear adst mov.b #h?f, rol mov.b rol, @h?fea ; disable external trigger mov.b #h?1, rol mov.b rol, @h?fe8 ; select mode and channel and set adst to "1" value set in adcsr: (2) the a/d converter converts the voltage level at the the an 1 input pin to a digital value. at the end of the conversion process the a/d converter transfers the result to register addrb, sets the adf bit is set to ?,?clears the adst bit to ?,? and halts. (3) adf = ??and adie = ?,?so an a/d interrupt is requested. (4) the user-coded a/d interrupt-handling routine is started. (5) the interrupt-handling routine reads the adcsr value, then writes a ??in the adf bit to clear this bit to ?. (6) the interrupt-handling routine reads and processes the a/d conversion result. (7) the routine ends. steps (2) to (7) can now be repeated by setting the adst bit to ??again. adf adie adst scan cks ch2 ch1 ch0 0 1 1 0 0 0 0 1 215 waiting a/d conver- sion waiting a/d conver- sion waiting waiting waiting waiting set* y clear* y a/d conversion starts y set* y y read result read result a/d conversion result a/d conversion result set* y clear* y y * indicates execution of a software instruction adst adf channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) addra addrb addrc addrd interrupt (adi) adie figure 10-3. a/d operatio n in single m ode (when cha nnel 1 is sel ected) 216 10.3.2 scan mode (scan = 1) the scan mode can be used to monitor analog inputs on one or more channels. when the adst bit is set to ?,?either by software or by a high-to-low transition of the adtrg signal (if enabled), a/d conversion starts from the first channel selected by the ch bits. when ch2 = ??the first channel is an 0 . when ch2 = ??the first channel is an 4 . if the scan group includes more than one channel (i.e. if bit ch1 or ch0 is set), conversion of the next channel begins as soon as conversion of the first channel ends. conversion of the selected channels continues cyclically until the adst bit is cleared to ?.? the conversion results are placed in the data registers corresponding to the selected channels. the a/d data registers are readable by the cpu. before selecting the scan mode, clock, and analog input channels, software should clear the adst bit to ??to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. a/d conversion begins when the adst bit is set to "1" again. the same instruction can be used to alter the mode and channel selection and set adst to "1." the following example explains the a/d conversion process when three channels in group 0 are selected (an 0 , an 1 , and an 2 ) and the external trigger is disabled. figure 10-4 shows the corresponding timing chart. (1) software clears the adst bit to ?,?then selects the scan mode (scan = ??, scan group 0 (ch2 = ??, and analog input channels an0 to an2 (ch1 and ch0 = ?? and sets the adst bit to ??to start a/d conversion. coding example: (with slow clock and adi interrupt enabled) bclr #5, @h?fe8 ; clear adst mov.b #h?f, rol mov.b rol, @h?fea ; disable external trigger mov.b #h?2, rol mov.b rol, @h?fe8 ; select mode and channels and set adst to "1" value set in adcsr adf adie adst scan cks ch2 ch1 ch0 0 1 1 1 0 0 1 0 217 (2) the a/d converter converts the voltage level at the an 0 input pin to a digital value, and transfers the result to register addra. (3) next the a/d converter converts an 1 and transfers the result to addrb. then it converts an 2 and transfers the result to addrc. (4) after all selected channels (an 0 to an 2 ) have been converted, the ad converter sets the adf bit to ?.? if the adie bit is set to ?,?an a/d interrupt (adi) is requested. then the a/d converter begins converting an 0 again. (5) steps (2) to (4) are repeated cyclically as long as the adst bit remains set to ?. to stop the a/d converter, software must clear the adst bit to ?. regardless of which channel is being converted when the adst bit is cleared to ?,?when the adst bit is set to ??again, conversion begins from the the first selected channel (an 0 or an 4 ). 218 adst adf channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) addra addrb addrc addrd continuous a/d conversion set clear clear a/d conversion time waiting a/d conver- sion waiting a/d conver- sion ? waiting waiting a/d conver- sion waiting a/d conver- sion waiting waiting a/d conver- sion a waiting waiting transfer a/d conver- sion result a/d conversion result ? a/d conversion result a/d conversion result a y y y ? * 2 * 1 * 1 * 1 indicates execution of a software instruction y * 2 * 1 data undergoing conversion when adst bit is cleared are ignored. figure 10-4. a/d operatio n in scan mod e (when chann els 0 to 2 ar e selected) 219 note: if the adst bit is cleared to "0" when two or more channels are selected in the scan mode, incorrect values may be left in the a/d data registers. for this reason, in the scan mode the a/d data registers should be read while the adst bit is still set to "1." example: the following coding example sets up a four-channel a/d scan, and shows the first part of an adi interrupt handler for reading the converted data. note that the data are read before the adst bit is cleared. mov.b #5b , r0l mov.b r0l , @adcsr ; four-channel scan mode bset #5 , @adcsr ; start conversion (set adst) (conversion of four channels) adi: mov.b @addra , r1 ; read addra mov.b @addrb , r2 ; read addrb mov.b @addrc , r3 ; read addrc mov.b @addrd , r4 ; read addrd bclr #5 , @adcsr ; clear adst bclr #7 , @adcsr ; clear adf (it is not necessary to clear the adst bit in order to read addra to addrd.) 10.3.3 input sampling time and a/d conversion time the a/d converter includes a built-in sample-and-hold circuit. sampling of the input starts at a time t d after the adst bit is set to "1." the sampling process lasts for a time t spl . the actual a/d conversion begins after sampling is completed. figure 10-5 shows the timing of these steps. table 10-4 (a) lists the conversion times for the single mode. table 10-4 (b) lists the conversion times for the scan mode. the total conversion time (t conv ) includes t d and t spl . the purpose of t d is to synchronize the adcsr write time with the a/d conversion process, so the length of t d is variable. the total conversion time therefore varies within the minimum to maximum ranges indicated in table 10-4 (a) and (b). 220 in the scan mode, the ranges given in table 10-4 (b) apply to the first conversion. the length of the second and subsequent conversion processes is fixed at 256 states (when cks = "0") or 128 states (when cks = "1"). figure 10-5. a/d conversion timing internal address bus write signal input sampling timing adf t d t spl (1) (2) t conv (notation) (1) adcsr write cycle (2) adcsr address t d synchronization delay t spl input sampling time t conv total a/d conversion time 221 table 10-4 (a). a/d conversion time (single mode) table 10-4 (b). a/d conversion time (scan mode) note: values in the tables above are numbers of states. 10.3.4 external trigger input timing a/d conversion can be started by external trigger input at the adtrg pin. this input is enabled or disabled by the trge bit in the a/d control register (adcr). if the trge bit is set to "1," when a falling edge of adtrg is detected the adst bit is set to "1" and a/d conversion begins. subsequent operation is the same as when the adst bit is set to "1" by software. figure 10-6 shows the trigger timing. figure 10-6. external trigger input timing cks = "0" cks = "1" item symbol min typ max min typ max synchronization delay t d 18 33 10 17 input sampling time t spl 63 31 total a/d conversion time t conv 227 242 115 122 cks = "0" cks = "1" item symbol min typ max min typ max synchronization delay t d 18 33 10 17 input sampling time t spl 63 31 total a/d conversion time t conv 259 274 131 138 adtrg internal trigger signal adst a/d conversion 222 10.4 interrupts the a/d conversion module generates an a/d-end interrupt request (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in the a/d control/status register (adcsr). 223 section 11. dual-port ram (parallel communication interface) 11.1 overview the h8/330 has an on-chip dual-port ram (dpram) that can be accessed by both the cpu on the h8/330 chip and a master cpu on another chip. the dual-port ram can be used only in the single-chip mode (mode 3), and only when the dpme bit in the system control register (syscr) is set to "1." the dual-port-ram-enabled mode is called slave mode because it is designed for a master-slave system in which the dual-port ram provides a parallel communication interface with a master cpu. in this section the cpu on the h8/330 chip will be referred to as the h8/300 cpu. 11.1.1 features 15-byte capacity fifteen 8-bit parallel communication data registers standard external memory interface the master cpu can be connected to the dual-port ram in the same way as to a memory chip. simple data-transfer protocol can generate master cpu interrupts 225 11.1.2 block diagram figure 11-1 shows a block diagram of the dual-port ram. figure 11-1. block diagram of dual-port ram module data bus bus interface cs oe we rdy bus interface mwei mrei pccsr: parallel communication control/status register pcdr0: parallel communication data register 0 pcdr1 to 14 : paralle communication data register 1 to 14 p c c s r p c d r 0 a ddb 7 to ddb 0 rs3 to rs0 internal data bus p c d r 0 b p c d r 1 p c d r to 14 226 11.1.3 input and output pins table 11-1 lists the input and output pins of the dual-port ram. table 11-1. dual-port ram input and output pins * nmos open drain output. 11.1.4 register configuration table 11-2 lists the registers of the dual-port ram. table 11-2. dual-port ram register configuration name abbreviation i/o function dpram data bus ddb 7 to ddb 0 input/output an 8-bit parallel data bus by which the master cpu can access the dual-port ram. chip select cs input chip select input pin for selecting the dual-port ram. register select rs 3 to rs 0 input dual-port ram address input. output enable oe input enables output on the dpram data bus. write enable we input enables data to be written in the dual-port ram via the dpram data bus. ready rdy output * indicates that the dual-port ram is ready to be written or read by the master cpu. (nmos open-drain output) read/write h8/300 master initial on-chip external address name abbr. cpu cpu value address rs 3 rs 2 rs 1 rs 0 parallel communication pccsr r/(w)* r/(w)* h?0 h?ff0 0 0 0 0 control/status register parallel communication pcdr0a r w undeter- h?ff1 0 0 0 1 data register 0 pcdr0b w r mined h?ff1 0 0 0 1 parallel communication pcdr1 r/w r/w undeter- h?ff2 0 0 1 0 data register 1 mined parallel communication pcdr2 r/w r/w undeter- h?ff3 0 0 1 1 data register 2 mined parallel communication pcdr3 r/w r/w undeter- h?ff4 0 1 0 0 data register 3 mined 227 table 11-2. dual-port ram register configuration (cont.) note: the h8/300 cpu can write only bits 6, 4, and 2 of the pccsr. the master cpu can write only bit 4. 11.2 register descriptions 11.2.1 dual port ram enable bit (dpme) the dual-port ram is enabled or disabled by the dpram enable (dpme) bit in the system control register (syscr). in the extended modes the dual-port ram is always disabled. in the single-chip mode, the dual-port ram is initially disabled but can be enabled by setting the dpme bit to "1." read/write h8/300 master initial on-chip external address name abbr. cpu cpu value address rs 3 rs 2 rs 1 rs 0 parallel communication pcdr4 r/w r/w undeter- h?ff5 0 1 0 1 data register 4 mined parallel communication pcdr5 r/w r/w undeter- h?ff6 0 1 1 0 data register 5 mined parallel communication pcdr6 r/w r/w undeter- h?ff7 0 1 1 1 data register 6 mined parallel communication pcdr7 r/w r/w undeter- h?ff8 1 0 0 0 data register 7 mined parallel communication pcdr8 r/w r/w undeter- h?ff9 1 0 0 1 data register 8 mined parallel communication pcdr9 r/w r/w undeter- h?ffa 1 0 1 0 data register 9 mined parallel communication pcdr10 r/w r/w undeter- h?ffb 1 0 1 1 data register 10 mined parallel communication pcdr11 r/w r/w undeter- h?ffc 1 1 0 0 data register 11 mined parallel communication pcdr12 r/w r/w undeter- h?ffd 1 1 0 1 data register 12 mined parallel communication pcdr13 r/w r/w undeter- h?ffe 1 1 1 0 data register 13 mined parallel communication pcdr14 r/w r/w undeter- h?fff 1 1 1 1 data register 14 mined 228 system control register (syscr)??fc4 the only bit in the system control register that concerns the dual-port ram is the dpme bit. see section 2.4.2, "system control register" for the other bits. bit 1 ?dual-port ram enable (dpme): this bit enables or disables the dual-port ram. the dual-port ram can be enabled only in the single-chip mode (mode 3). if the dpme bit is set to ??while the h8/330 is operating in the single-chip mode, the following pins are automatically assigned to dual-port ram functions, regardless of their data direction register settings: port 3 (p3 7 to p3 0 ) ? ddb 7 to ddb 0 (parallel communication data bus; input/output) port 8 (p8 3 to p8 0 ) ? rs3 to rs0 (dual-port ram register select; input) in port 9, p9 7 ? we (write enable; input) p95 ? rdy (ready; output) p9 4 ? oe (output enable; input) p9 3 ? cs (chip select; input) the dpme bit is initialized to ??by a reset and in the hardware standby mode. setting the dpme bit to "1" in the expanded modes (modes 1 and 2) has no effect. bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg dpme rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w bit 1 dpme description 0 the dual-port ram is disabled. (initial value) 1 the dual-port ram is enabled (in single-chip mode only). 229 11.2.2 parallel communication data register 0 (pcdr0) ?h?ff1 (a) parallel communication data register 0a (pcdr0a) (b) parallel communication data register 0b (pcdr0b) parallel communication data register 0 consists of two separate 8-bit registers with the same address. as shown in figure 11-2, pcdr0a is written by the h8/300 cpu and read by the master cpu; pcdr0b is written by the master cpu and read by the h8/300 cpu. this arrangement prevents contention even if both cpus write to pcdr0 at the same time. when either cpu reads pcdr0, it is assured of reading data written by the other cpu. figure 11-2. parallel communication data register 0 bit 7 6 5 4 3 2 1 0 initial value r/w h8/300 cpu w w w w w w w w master cpu r r r r r r r r internal data bus h8/300 cpu read write pcdr0a pcdr0b external data bus master cpu write read pcdr 0 bit 7 6 5 4 3 2 1 0 initial value r/w h8/300 cpu r r r r r r r r master cpu w w w w w w w w 230 the value in pcdr0 after a reset is undetermined. in non-slave modes, the value obtained by reading pcdr0 is unpredictable. 11.2.3 parallel communication data registers 1 to 14 ?h?ff2 (pcdr1) to h?fff (pcdr1-14) parallel communication data registers 1 to 14 are 8-bit registers which can be written and read by either the h8/300 cpu or the master cpu. the h8/300 cpu can read and write these registers regardless of the operating mode of the h8/330 chip. the master cpu can read and write them only when the h8/330 chip is operating in slave mode. in non-slave modes, these registers can be used as 14 bytes of data memory. note that access requires three states per byte, which is slower than the on-chip ram. the values in pcdr1 to pcdr14 after a reset are undetermined. 11.2.4 parallel communication control/status register (pccsr) ?h?ff0 the pccsr is an 8-bit readable and partly writable register that provides protocol and interrupt control functions. either cpu can read and write bit 4, which enables the rdy signal. the h8/300 cpu can read and write bits 6, 4 and 2, which enable interrupts. the other bits are read- only bits. the pccsr is initialized to h?0 at a reset and in the standby modes. bit 7 6 5 4 3 2 1 0 initial value r/w h8/300 cpu r/w r/w r/w r/w r/w r/w r/w r/w master cpu r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 mwef emwi swef eakar mref emri mwmf swmf initial value 0 0 0 0 0 0 0 0 r/w h8/300 cpu r r/w r r/w r r/w r r master cpu r r r r/w r r r r 231 in the bit names that follow, the h8/300 is referred to as the slave and the master cpu as the master. bit 7 ?master write end flag (mwef): this flag bit is used to indicate that the master cpu has finished writing data in the parallel communication data registers. it is set when the master cpu writes to pcdr14 and cleared when the h8/300 cpu reads pcdr14. bit 6 ?enable master write interrupt (emwi): this bit enables or disables the master write end interrupt (mwei). bit 5 ?slave write end flag (swef): this flag bit is used to indicate that the h8/300 cpu has finished writing data in the parallel communication data registers. it is set when the h8/300 cpu writes to pcdr14 and cleared when the master cpu reads pcdr14. bit 4 ?enable acknowledge and request (eakar): this bit enables or disables the rdy signal output by the h8/330 chip. if enabled: the rdy signal goes low when the h8/300 cpu reads pcdr0 while the dual-port ram is in the master write mode (mwmf = "1"), or when the h8/300 cpu writes to pcdr14. the rdy signal goes high when the master cpu reads pcdr14 or the pccsr, or when either the master or h8/300 cpu writes to pcdr0. in the non-slave modes this bit has no effect. bit 7 mwef description 0 the h8/300 cpu has read pcdr14 while the dual-port (initial state) ram was in the master write mode (mwmf = "1"). 1 the master cpu has written data in pcdr14. bit 6 emwi description 0 the master write end interrupt request (mwei) is disabled. (initial state) 1 the master write end interrupt request (mwei) is enabled. bit 5 swef description 0 the master cpu has read pcdr14. (initial state) 1 the h8/300 cpu has written data in pcdr14. 232 bit 3 ?master read end flag (mref): this flag indicates whether the master cpu has finished reading data set in the parallel communication data registers. bit 2 ?enable master read interrupt (emri): this bit enables or disables the master read end interrupt (mrei). bit 1 ?master write mode flag (mwmf): this bit indicates when the dual-port ram is in the master write mode. the master cpu should check that this bit is set to ??before writing to parallel communication data registers 1 to 14. the h8/300 cpu cannot write in those registers while this bit is set to ?. bit 4 eakar description 0 rdy output is disabled. rdy remains in the high-impedance state. (initial state) 1 rdy output is enabled. bit 3 mref description 0 this bit is cleared to ??when: (initial state) the h8/300 cpu reads or writes pcdr0. the master cpu writes to pcdr0. 1 this bit is set to ??when the master cpu reads pcdr0. bit 2 emri description 0 the master read end interrupt request (mrei) is disabled. (initial state) 1 the master read end interrupt request (mrei) is enabled. bit 1 mwmf description 0 this bit is cleared to ??when the h8/300 cpu reads pcdr0. (initial state) the dual-port ram is not in the master write mode. the master cpu should avoid writing in pcdr1 to pcdr14. 1 this bit is set to ??if the master cpu writes to pcdr0 while the swmf flag is cleared to ?.? the dual-port ram is in the master write mode. only the master cpu can write in pcdr1 to pcdr14. 233 bit 0 ?slave write mode flag (swmf): this bit indicates when the dual-port ram is in the slave write mode. the h8/300 cpu should check that this bit is set to ??before writing to parallel communication data registers 1 to 14. the master cpu cannot write in those registers while this bit is set to ?. 11.3 usage the dual-port ram has a simple protocol for controlling the use of the data registers and parallel communication data bus. the basic rule is that when either cpu writes to the dual-port ram, it should write to pcdr0 first and pcdr14 last. conversely, in reading the dual-port ram, the cpu should read pcdr14 first and pcdr0 last. procedures for data transfer in both directions are given below. figure 11-3 shows a timing chart. 11.3.1 data transfer from master cpu to h8/300 cpu the following procedure should be used when the master cpu sends data to the h8/300 cpu via the dual-port ram: (1) the master cpu writes the first byte of data in pcdr0. if the dual-port ram is not currently in the slave write mode, mwmf is set to "1," placing it in the master write mode and preventing the h8/300 cpu from writing in pcdr1 to pcdr14. (2) the master cpu reads the pccsr and checks mwmf. if mwmf is set to ?,?the master cpu may continue writing in pcdr1 to pcdr14. if mwmf is cleared to "0," the dual-port ram is presumably in the slave write mode. (3) the master cpu writes data in pcdr1 to pcdr13 as required, then writes the last byte in pcdr14. this sets the master write end flag (mwef) to ?,?notifying the h8/300 cpu that the master cpu has finished writing. if emwi is set to ?,?a master write end interrupt is requested. bit 0 swmf description 0 this bit is cleared to ??when the master cpu reads pcdr0. (initial state) the dual-port ram is not in the slave write mode. the h8/300 cpu should avoid writing in pcdr1 to pcdr14. 1 this bit is set to ??if the h8/300 cpu writes to pcdr0 while the mwmf flag is cleared to ?.? the dual-port ram is in the slave write mode. only the h8/300 cpu can write in pcdr1 to pcdr14. 234 (4) after the master cpu has finished writing data, the h8/300 cpu first reads pcdr14. this clears the master write end flag. then the h8/300 cpu reads data from pcdr1 to pcdr13 as required. finally, the h8/300 cpu reads pcdr0. this clears mwmf, so the dual-port ram is no longer in the master write mode. if the eakar bit is set to ?,?the rdy signal goes low to acknowledge the received data. (5) if the master cpu has more data to send, it should check that mwmf is cleared to "0," then repeat the above procedure from step (1). if mwmf is still set to "1," that indicates that the h8/300 cpu has not read all the data sent previously. 11.3.2 data transfer from h8/300 cpu to master cpu the following procedure should be used when the h8/300 cpu sends data to the master cpu via the dual-port ram: (1) the h8/300 cpu writes the first byte of data in pcdr0. if the dual-port ram is not currently in the master write mode, swmf is set to "1," placing it in the slave write mode and preventing the master cpu from writing in pcdr1 to pcdr14. (2) the h8/300 cpu reads the pccsr and checks swmf. if swmf is set to ?,?the h8/300 cpu may continue writing in pcdr1 to pcdr14. if swmf is cleared to "0," the dual-port ram is presumably in the master write mode. (3) the h8/300 cpu writes data in pcdr1 to pcdr13 as required, then writes the last byte in pcdr14. this sets the slave write end flag (swef) to ?.? if the eakar bit is set to ?, the rdy signal goes low to notify the master cpu that the h8/300 cpu has finished writing. (4) after the h8/300 cpu has finished writing data, the master cpu first reads pcdr14. this clears the slave write end flag. then the master cpu reads data from pcdr1 to pcdr13 as required. finally, the master cpu reads pcdr0. this clears the swmf bit, so the dual-port ram is no longer in the slave write mode. it also sets the master read end flag (mref). if emri is set to ?,?a master read end interrupt is requested to notify the h8/300 cpu that the master cpu has finished reading the data. (5) if the h8/300 cpu has more data to send, it should check that swmf is cleared to "0," then repeat the above procedure from step (1). if swmf is still set to "1," that indicates that the master cpu has not read all the data sent previously. 235 h8/300 cpu slave receive mode write pcdr0 write pcdr14 read pcdr14 read pcdr0 write pcdr0 read pccsr write pcdr14 read pcdr14 read pcdr0 master cpu swmf mwmf mwef swef (rdy) h8/300 cpu master cpu swmf mwmf mwef swef (rdy) mref mref slave transmit mode write pcdr0 write pcdr14 read pccsr read pcdr14 read pcdr0 write pcdr0 read pcdr14 read pcdr0 read pccsr read pccsr write pcdr14 figure 11-3. dual-port ram timing chart 236 11.4 master-slave interconnections figure 11-4 shows an example of the master-slave interconnections when the master chip is an h8/532. figure 11-4. interconnection to h8/532 (example) decoder data bus address bus a 15 ?a 4 a 3 ?a 0 d 7 ?d 0 wr rd irq cs rs 3 ?rs 0 ddb 7 ?ddb 0 we oe rdy h8/532 h8/330 note: an external pull-up resistor should be connected to the rdy output pin. 237 section 12. ram 12.1 overview the h8/330 includes 512 bytes of on-chip static ram, connected to the cpu by a 16-bit data bus. both byte and word access to the on-chip ram are performed in two states, enabling rapid data transfer and instruction execution. the on-chip ram is assigned to addresses h?d80 to h?f7f in the chip s address space. the rame bit in the system control register (syscr) can enable or disable the on-chip ram, permitting these addresses to be allocated to external memory instead, if so desired. 12.2 block diagram figure 12-1 is a block diagram of the on-chip ram. figure 12-1. block diagram of on-chip ram 12.3 ram enable bit (rame) the on-chip ram is enabled or disabled by the rame (ram enable) bit in the system control register (syscr). table 12-1 lists information about the system control register. h'ff7e internal data bus (lower 8 bits) address h'fd82 h'fd80 internal data bus (upper 8 bits) h'ff7f h'ff7e h'fd82 h'fd80 h'fd83 h'fd81 even address odd address on-chip ram 239 table 12-1. system control register the only bit in the system control register that concerns the on-chip ram is the rame bit. see section 2.4.2, "system control register" for the other bits. bit 0 ?ram enable (rame): this bit enables or disables the on-chip ram. the rame bit is initialized to ??on the rising edge of the res signal, so a reset enables the on- chip ram. the rame bit is not initialized in the software standby mode. 12.4 operation 12.4.1 expanded modes (modes 1 and 2) if the rame bit is set to ?,?accesses to addresses h?d80 to h?f7f are directed to the on-chip ram. if the rame bit is cleared to ?,?accesses to addresses h?d80 to h?f7f are directed to the external data bus. 12.4.2 single-chip mode (mode 3) if the rame bit is set to ?,?accesses to addresses h?d80 to h?f7f are directed to the on-chip ram. if the rame bit is cleared to ?,?the on-chip ram data cannot be accessed. attempted write access has no effect. attempted read access always results in h?f data being read. name abbreviation r/w initial value address system control register syscr r/w h?9 h?fc4 bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg dpme rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w bit 7 rame description 0 on-chip ram is disabled. 1 on-chip ram is enabled. (initial value) 240 section 13. rom 13.1 overview the h8/330 includes 16k bytes of high-speed, on-chip rom. the on-chip rom is connected to the cpu via a 16-bit data bus. both byte data and word data are accessed in two states, enabling rapid data transfer and instruction fetching. the h8/330 is available in two versions: one with electrically programmable rom (prom); the other with masked rom. the prom version has a prom mode in which the chip can be programmed with a standard prom writer. the on-chip rom is enabled or disabled depending on the mcu operating mode, which is determined by the inputs at the mode pins (md 1 and md 0 ) when the chip comes out of the reset state. see table 13-1. table 13-1. on-chip rom usage in each mcu mode mode pins mode md 1 md 0 on-chip rom mode 1 (expanded mode) 0 1 disabled (external addresses) mode 2 (expanded mode) 1 0 enabled mode 3 (single-chip mode) 1 1 enabled 241 13.1.1 block diagram figure 13-1 is a block diagram of the on-chip rom. figure 13-1. block diagram of on-chip rom 13.2 prom mode 13.2.1 prom mode setup in the prom mode of the prom version of the h8/330, the usual microcomputer functions are halted to allow the on-chip prom to be programmed. the programming method is the same as for the hn27c256. to select the prom mode, apply the signal inputs listed in table 13-2. table 13-2. selection of prom mode h'0002 h'0000 internal data bus (lower 8 bits) internal data bus (upper 8 bits) h'0003 h'0001 h'3fff h'3ffe on-chip rom even addresses odd addresses pin input mode pin md 1 low mode pin md 0 low stby pin low pins p8 0 and p8 1 high 242 13.2.2 socket adapter pin assignments and memory map the h8/330 can be programmed with a general-purpose prom writer. since the h8/330 package has 80 or 84 pins instead of 28, a socket adapter is necessary. table 13-3 lists recommended socket adapters. figure 13-2 shows the socket adapter pin assignments by giving the correspondence between h8/330 pins and hn27c256 pin functions. figure 13-3 shows a memory map in the prom mode. since the h8/330 has only 16k bytes of on-chip prom, the address range should be specified as h?000 to h?fff. h?f data should be specified for unused address areas. it is important to limit the program address range to h'0000 to h'3fff and specify h'ff data for h'4000 and higher addresses. if data (other than h?f) are written by mistake in addresses equal to or greater than h?000, it may become impossible to program or verify the prom data. with a windowed package, it is possible to erase the data and reprogram, but this cannot be done with a plastic package, so particular care is required. table 13-3. recommended socket adapters package recommended socket adapter 84-pin plcc hs338esc01h 84-pin windowed lcc hs338esg01h 80-pin qfp hs338esh01h 243 figure 13-2. socket adapter pin assignments fp-80a cg-84, pin pin hn27c256h cp-84 1 12 res v pp 1 6 17 nmi ea 9 24 65 79 p3 0 eo 0 11 66 80 p3 1 eo 1 12 67 81 p3 2 eo 2 13 68 82 p3 3 eo 3 15 69 83 p3 4 eo 4 16 70 84 p3 5 eo 5 17 71 1 p3 6 eo 6 18 72 3 p3 7 eo 7 19 64 78 p1 0 ea 0 10 63 77 p1 1 ea 1 9 62 76 p1 2 ea 2 8 61 75 p1 3 ea 3 7 60 74 p1 4 ea 4 6 59 73 p1 5 ea 5 5 58 72 p1 6 ea 6 4 57 71 p1 7 ea 7 3 55 69 p2 0 ea 8 25 54 68 p2 1 oe 22 53 67 p2 2 ea 10 21 52 66 p2 3 ea 11 23 51 65 p2 4 ea 12 2 50 63 p2 5 ea 13 26 49 62 p2 6 ea 14 27 48 61 p2 7 ce 20 74 5 p8 0 v cc 28 75 6 p8 1 29 42 av cc 8 19 v cc 47 60 v cc 5 16 md 0 v ss 14 4 15 md 1 7 18 stby 38 51 av ss 12 2 v ss 56 4 v ss 73 23 v ss 24 v ss 41 v ss 64 v ss 70 v ss notation v pp : programming voltage (12.5 v) eo 7 to eo 0 : data input/output ea 14 to ea 0 : address input oe: output enable ce: chip enable note: all pins not listed in this figure should be left open. h8/330 eprom socket 244 figure 13-3. memory map in prom mode 13.3 programming the write, verify, inhibited, and read sub-modes of the prom mode are selected as shown in table 13-4. table 13-4. selection of sub-modes in prom mode note: the v pp and v cc pins must be held at the v pp and v cc voltage levels. the h8/330 prom uses the same, standard read/write specifications as the hn27c256 and hn27256. 13.3.1 writing and verifying an efficient, high-speed programming procedure can be used to write and verify prom data. this procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. it leaves the data h?f written in unused addresses. h'3fff h'3fff "1" output * * if this area is read in prom mode, the output data are h'ff. h'7fff address in prom mode address in mcu mode h'0000 h'0000 on-chip prom pins sub-mode ce oe v pp v cc eo 7 ?eo 0 ea 14 ?ea 0 write low high v pp v cc data input address input verify high low v pp v cc data output address input programming inhibited high high v pp v cc high-impedance address input 245 figure 13-4 shows the basic high-speed programming flowchart. tables 13-5 and 13-6 list the electrical characteristics of the chip in the prom mode. figure 13-5 shows a write/verify timing chart. figure 13-4. high-speed programming flowchart start address = 0 n = 0 set read mode vcc = 5.0v 0.5v, vpp = vcc end y n y n y n < 25 all addresses read? error n y n + 1 ? n address + 1 ? address n last address? write time t = 1 ms 5% pw write t = 3n ms opw verify ok? set program/verify mode vcc = 6.0v 0.25v, vpp = 12.5v 0.5v figure 13-4 246 table 13-5. dc characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, v ss = 0v, ta = 25?c 5?c) table 13-6. ac characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, ta = 25?c 5?c) measurement item symbol min typ max unit conditions input high voltage eo 7 ?eo 0 , v ih 2.4 v cc + 0.3 v ea 14 ?ea 10 , ea 8 ?ea 0 , oe, ce ea 9 v cc 0.7 v cc + 0.3 v input low voltage eo 7 ?eo 0 , v il ?0.3 0.8 v ea14 ?ea 0 , oe, ce output high voltage eo 7 ?eo 0 v oh 2.4 v i oh = ?00 a output low voltage eo 7 ?eo 0 v ol 0.45 v i ol = 1.6ma input leakage eo 7 ?eo 0 , |i li | 2 a v in = 5.25v/ current ea 14 ?ea 0 , 0.5v oe, ce vcc current i cc 40 ma vpp current ipp 40 ma measurement item symbol min typ max unit conditions address setup time t as 2 s see figure 13-5* oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df 130 ns vpp setup time t vps 2 s program pulse width t pw 0.95 1.0 1.05 ms * input pulse level: 0.8v to 2.2v input rise/fall time 20ns timing reference levels: input?.0v, 2.0v; output?.8v, 2.0v < = 247 table 13-6. ac characteristics (cont.) (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, ta = 25?c 5?c) figure 13-5. prom write/verify timing * input pulse level: 0.8v to 2.2v input rise/fall time 20ns timing reference levels: input?.0v, 2.0v; output?.8v, 2.0v < = measurement item symbol min typ max unit conditions oe pulse width for t opw 2.85 78.75 ms see figure 13-5* overwrite-programming vcc setup time t vcs 2 s data output delay time t oe 0 500 ns oe ce write verify address data input data output data t vps t ds t dh t as t ah t df v pp v pp v cc v cc gnd t vcs t pw t opw t oes t oe v cc 248 13.3.2 notes on writing (1) write with the specified voltages and timing. the programming voltage (vpp) is 12.5v. caution: applied voltages in excess of the specified values can permanently destroy the chip. be particularly careful about the prom writer s overshoot characteristics. if the prom writer is set to intel specifications or hitachi hn27256 or hn27c256 specifications, v pp will be 12.5v. (2) before writing data, check that the socket adapter and chip are correctly mounted in the prom writer. overcurrent damage to the chip can result if the index marks on the prom writer, socket adapter, and chip are not correctly aligned. (3) don? touch the socket adapter or chip while writing. touching either of these can cause contact faults and write errors. 13.3.3 reliability of written data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150?c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 13-6 shows the recommended screening procedure. figure 13-6. recommended screening procedure write program read and check program vcc = 4.5v and 5.5v install baking time should be measured from the point when the baking oven reaches 150 c. note: bake with power off 150 10 c, 48 hr + 8 hr * ?0 hr 249 if a series of write errors occurs while the same prom writer is in use, stop programming and check the prom writer and socket adapter for defects, using a microcomputer chip with a windowed package and on-chip eprom. please inform hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 13.3.4 erasing of data the windowed package enables data to be erased by illuminating the window with ultraviolet light. table 13-7 lists the erasing conditions. table 13-7. erasing conditions the conditions in table 13-7 can be satisfied by placing a 12000 w/cm 2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes. 13.4 handling of windowed packages (1) glass erasing window: rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. if the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. this returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the prom, so it is recommended that the chip be reprogrammed afterward. accumulation of static charge on the window surface can be prevented by the following precautions: ? when handling the package, ground yourself. don t wear gloves. avoid other possible sources of static charge. - avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. item value ultraviolet wavelength 253.7 nm minimum illumination 15w?/cm 2 250 a be careful when using cooling sprays, since they may have a slight ion content. cover the window with an ultraviolet-shield label, preferably a label including a conductive material. besides protecting the prom contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. (2) handling after programming: fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. in addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. it is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). (3) note on 84-pin lcc package: a socket should always be used when the 84-pin lcc package is mounted on a printed-circuit board. table 13.8 lists the recommended socket. table 13-8. recommended socket for mounting 84-pin lcc package manufacturer code sumitomo 3-m 284-1273-00-1102j 251 section 14. power-down state 14.1 overview the h8/330 has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. the power-down state includes three modes: (1) sleep mode ?a software-triggered mode in which the cpu halts but the rest of the chip remains active (2) software standby mode ?a software-triggered mode in which the entire chip is inactive (3) hardware standby mode ?a hardware-triggered mode in which the entire chip is inactive table 14-1 lists the conditions for entering and leaving the power-down modes. it also indicates the status of the cpu, on-chip supporting modules, etc. in each power-down mode. table 14-1. power-down state notes 1. syscr: system control register 2. ssby: software standby bit 3. on-chip supporting modules, including the dual-port ram. entering cpu sup. i/o exiting mode procedure clock cpu reg s. mod.* ram ports methods sleep execute run halt held run held held interrupt mode sleep res instruction stby soft- set ssby bit halt halt held halt held held nmi ware in syscr to and irq 0 ?irq 2 standby ?,?then initial- stby mode execute sleep ized res instruction hard- set stby halt halt not halt held high stby high, ware pin to low held and impe- then res standby level initialized dance low ? high mode state 253 14.2 system control register: power-down control bits bits 7 to 4 of the system control register (syscr) concern the power-down state. specifically, they concern the software standby mode. table 14-2 lists the attributes of the system control register. table 14-2. system control register bit 7 ?software standby (ssby): this bit enables or disables the transition to the software standby mode. on recovery from the software standby mode by an external interrupt, ssby remains set to "1." to clear this bit, software must write a "0." bits 6 to 4 ?standby timer select 2 to 0 (sts2 to sts0): these bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. during the selected time, the clock oscillator runs but clock pulses are not supplied to the cpu or the on-chip supporting modules. name abbreviation r/w initial value address system control register syscr r/w h?9 h?fc4 bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg dpme rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w bit 7 ssby description 0 the sleep instruction causes a transition to the sleep mode. (initial value) 1 the sleep instruction causes a transition to the software standby mode. 254 when the h8/330's on-chip clock generator is used, the sts bits should be set to allow a settling time of at least 10ms. table 14-3 lists the settling times selected by these bits at several clock frequencies and indicates the recommended settings. when the h8/330 is externally clocked, the sts bits can be set to any value. the minimum value (sts2 = sts1 = sts0 = "0") is recommended. table 14-3. times set by standby timer select bits (unit: ms) notes: 1. all times are in milliseconds. 2. recommended values are printed in boldface. 14.3 sleep mode the sleep mode provides an effective way to conserve power while the cpu is waiting for an external interrupt or an interrupt from an on-chip supporting module. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 settling time = 8192 states (initial value) 0 0 1 settling time = 16384 states 0 1 0 settling time = 32768 states 0 1 1 settling time = 65536 states 1 settling time = 131072 states settling time system clock frequency (mhz) sts2 sts1 sts0 (states) 10 8 6 4 2 1 0.5 0 0 0 8192 0.8 1.0 1.3 2.0 4.1 8.2 16.4 0 0 1 16384 1.6 2.0 2.7 4.1 8.2 16.4 32.8 0 1 0 32768 3.3 4.1 5.5 8.2 16.4 32.8 65.5 0 1 1 65536 6.6 8.2 10.9 16.4 32.8 65.5 131.1 1 131072 13.1 16.4 21.8 32.8 65.5 131.1 262.1 255 14.3.1 transition to sleep mode when the ssby bit in the system control register is cleared to ?,?execution of the sleep instruction causes a transition from the program execution state to the sleep mode. after executing the sleep instruction, the cpu halts, but the contents of its internal registers remain unchanged. the on-chip supporting modules continue to operate normally. 14.3.2 exit from sleep mode the chip wakes up from the sleep mode when it receives an internal or external interrupt request, or a low input at the res or stby pin. (1) wake-up by interrupt: an interrupt releases the sleep mode and starts the cpu s interrupt- handling sequence. if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module s control register, the interrupt cannot be requested, so it cannot wake the chip up. similarly, the cpu cannot be awoken by an interrupt other than nmi if the i (interrupt mask) bit in the ccr (condition code register) is set when the sleep instruction is executed. (2) wake-up by res pin: when the res pin goes low, the chip exits from the sleep mode to the reset state. (3) wake-up by stby pin: when the stby pin goes low, the chip exits from the sleep mode to the hardware standby mode. 14.4 software standby mode in the software standby mode, the system clock stops and chip functions halt, including both cpu functions and the functions of the on-chip supporting modules. power consumption is reduced to an extremely low level. the on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained (at least 2v), the contents of the cpu registers and on-chip ram remain unchanged. 256 14.4.1 transition to software standby mode to enter the software standby mode, set the standby bit (ssby) in the system control register (syscr) to ?,?then execute the sleep instruction. 14.4.2 exit from software standby mode the chip can be brought out of the software standby mode by an input at one of six pins: nmi, irq 0 , irq 1 , irq 2 , res, or stby. (1) recovery by external interrupt: when an nmi, irq 0 , irq 1 , or irq 2 request signal is received, the clock oscillator begins operating. after the waiting time set in the system control register (bits sts2 to sts0), clock pulses are supplied to the cpu and on-chip supporting modules. the cpu executes the interrupt-handling sequence for the requested interrupt, then returns to the instruction after the sleep instruction. the ssby bit is not cleared. see section 14.2, ?ystem control register: power-down control bits?for information about the sts bits. interrupts irq 3 to irq 7 should be disabled before entry to the software standby mode. clear irq 3 e to irq 7 e to "0" in the interrupt enable register (ier). (2) recovery by res pin: when the res pin goes low, the clock oscillator starts. next, when the res pin goes high, the cpu begins executing the reset sequence. the ssby bit is cleared to ?. the res pin must be held low long enough for the clock to stabilize. (3) recovery by stby pin: when the stby pin goes low, the chip exits from the software standby mode to the hardware standby mode. 14.4.3 sample application of software standby mode in this example the h8/330 enters the software standby mode when nmi goes low and exits when nmi goes high, as shown in figure 14-1. 257 the nmi edge bit (nmieg) in the system control register is originally cleared to "0," selecting the falling edge. when nmi goes low, the nmi interrupt handling routine sets nmieg to "1," sets ssby to "1" (selecting the rising edge), then executes the sleep instruction. the h8/330 enters the software standby mode. it recovers from the software standby mode on the next rising edge of nmi. figure 14-1. software standby mode (when) nmi timing 14.4.4 application notes (1) the i/o ports retain their current states in the software standby mode. if a port is in the high output state, the current dissipation caused by the high output current is not reduced. (2) if the software standby mode is entered under either condition ? or condition below, current dissipation is greater than in normal standby mode. ? in single-chip mode (mode 3): if software standby mode is entered by executing an instruction stored in on-chip rom, after even one instruction not stored in on-chip rom has been fetched (e.g. from on-chip ram). in expanded mode with on-chip rom enabled (mode 2): if software standby mode is entered by executing an instruction stored in on-chip rom, after even one instruction not stored in on-chip rom has been fetched (e.g. from external memory or on-chip ram). clock generator nmi ssby nmieg settling time nmi interrupt handler nmieg = "1" ssby = "1" software standby mode (power-down state) nmi interrupt handler sleep 258 note that the h8/300 cpu pre-fetches instructions. if an instruction stored in the last two bytes of on-chip rom is executed (at addresses h'3ffe and h'3fff in the h8/330), the contents of the next two bytes (h'4000 and h'4001), which are not in on-chip rom, will be fetched as the next instruction. this problem does not occur in expanded mode when on-chip rom is disabled (mode 1). in hardware standby mode there is no such additional current dissipation, regardless of the conditions when hardware standby mode is entered. 14.5 hardware standby mode 14.5.1 transition to hardware standby mode regardless of its current state, the chip enters the hardware standby mode whenever the stby pin goes low. the hardware standby mode reduces power consumption drastically by halting the cpu, stopping all the functions of the on-chip supporting modules, and placing i/o ports in the high-impedance state. the registers of the on-chip supporting modules are reset to their initial values. only the on- chip ram is held unchanged, provided the minimum necessary voltage supply is maintained (at least 2v). notes: 1. the rame bit in the system control register should be cleared to ??before the stby pin goes low, to disable the on-chip ram during the hardware standby mode. 2. do not change the inputs at the mode pins (md1, md0) during hardware standby mode. be particularly careful not to let both mode pins go low in hardware standby mode, since that places the chip in prom mode and increases current dissipation. 14.5.2 recovery from hardware standby mode recovery from the hardware standby mode requires inputs at both the stby and res pins. when the stby pin goes high, the clock oscillator begins running. the res pin should be low at this time and should be held low long enough for the clock to stabilize. when the res pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. 259 14.5.3 timing relationships figure 14-2 shows the timing relationships in the hardware standby mode. in the sequence shown, first res goes low, then stby goes low, at which point the h8/330 enters the hardware standby mode. to recover, first stby goes high, then after the clock settling time, res goes high. figure 14-2. hardware standby mode timing clock pulse generator res stby clock settling time result 260 section 15. e-clock interface 15.1 overview for interfacing to peripheral devices that require it, the h8/330 can generate an e clock output. special instructions (movtpe, movfpe) perform data transfers synchronized with the e clock. the e clock is created by dividing the system clock ( ) by 8. the e clock is output at the p8 0 pin when the p8 0 ddr bit in the port 8 data direction register (p8ddr) is set to ?.? it is output only in the expanded modes (mode 1 and mode 2); it is not output in the single-chip mode. output begins immediately after a reset. when the cpu executes an instruction that synchronizes with the e clock, the address strobe (as), the address on the address bus, and the ios signal are output as usual, but the rd and wr signal lines and the data bus do not become active until the falling edge of the e clock is detected. the length of the access cycle for an instruction synchronized with the e clock accordingly varies from 9 to 16 states. figures 15-1 and 15-2 show the timing in the cases of maximum and minimum synchronization delay. it is not possible to insert wait states (t w ) during the execution of an instruction synchronized with the e clock by input at the wait pin. 261 figure 15-1. execution cycle of instruction synchronized with e clock in expanded modes (maximum synchronization delay) 262 figure 15-2. execution cycle of instruction synchronized with e clock in expanded modes (minimum synchronization delay) 263 section 16. clock pulse generator 16.1 overview the h8/330 chip has a built-in clock pulse generator (cpg) consisting of an oscillator circuit, a system ( ) clock divider, an e clock divider, and a prescaler. the prescaler generates clock signals for the on-chip supporting modules. 16.1.1 block diagram figure 16-1. block diagram of clock pulse generator 16.2 oscillator circuit if an external crystal is connected across the extal and xtal pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. alternatively, an external clock signal can be applied to the extal pin. (1) connecting an external crystal ? circuit configuration: an external crystal can be connected as in the example in figure 16-2. an at-cut parallel resonating crystal should be used. xtal extal e /2 to /4096 prescaler oscillator circuit 2 divider 8 divider cpg 265 figure 16-2. connection of crystal oscillator (example) - crystal oscillator: the external crystal should have the characteristics listed in table 16-1. table 16-1. external crystal parameters frequency (mhz) 2 4 8 12 16 20 rs max ( ) 500 120 60 40 30 20 c 0 (pf) 7 pf max figure 16-3. equivalent circuit of external crystal a note on board design: when an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. see figure 16-4. the crystal and its load capacitors should be placed as close as possible to the xtal and extal pins. extal xtal c l1 c l1 = c l2 = 10 to 22pf c l2 c l c 0 xtal extal l r s at-cut parallel resonating crystal 266 figure 16-4. notes on board design around external crystal (2) input of external clock signal ? circuit configuration: an external clock signal can be input at the extal pin. the reverse- phase clock signal should be input at the xtal pin, as shown in the example in figure 16-5. figure 16-5. external clock input (example) - external clock input extal xtal external clock input 74hc04 frequency double the system clock ( ) frequency duty factor 45% to 55% not allowed signal a signal b h8/330 xtal extal c l1 c l2 267 16.3 system clock divider the system clock divider divides the crystal oscillator or external clock frequency by 2 to create the system clock ( ). an e clock signal is created by dividing the system clock by 8. figure 16-6 shows the phase relationship of the e clock to the system clock. figure 16-6. phase relationship of system clock and e clock e 268 section 17. electrical specifications 17.1 absolute maximum ratings table 17-1 lists the absolute maximum ratings. table 17-1. absolute maximum ratings item symbol rating unit supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.5 v input voltage ports 1 ?6, 8, 9 v in ?.3 to v cc + 0.3 v port 7 v in ?.3 to av cc + 0.3 v analog supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?0 to +75 ?c wide-range specifications: ?40 to +85 ?c storage temperature t stg ?5 to +125 ?c note: the input pins have protection circuits that guard against high static voltages and electric fields, but these high input-impedance circuits should never receive overvoltages exceeding the absolute maximum ratings shown in table 17-1. 17.2 electrical characteristics 17.2.1 dc characteristics table 17-2 lists the dc characteristics of the h8/330. 269 table 17-2. dc characteristics conditions: v cc = 5.0v 10%*, av cc = 5.0v 10%, v ss = av ss = 0v, t a = ?0 to 75?c (regular specifications), t a = ?0 to 85?c (wide-range specifications) measurement item symbol min typ max unit conditions schmitt trigger p6 7 ?p6 2 , p6 0 , v t - 1.0 v input voltage p8 6 ?p8 0 , v t + 3.5 v (1) p9 7 , p9 4 ?p9 0 v t + ? t - 0.4 v input high voltage res, stby , v ih v cc ?0.7 v cc + 0.3 v (2) md 1 , md 0 extal, nmi v cc 0.7 v cc + 0.3 v p7 7 ?p7 0 2.2 av cc + 0.3 v input high voltage input pins v ih 2.2 v cc + 0.3 v other than (1) and (2) input low voltage res, stby v il ?.3 0.5 v (3) md 1 , md 0 input low voltage input pins v il ?.3 0.8 v other than (1) and (3) output high all output pins v oh v cc ?0.5 v i oh = ?00 a voltage 3.5 v i oh = ?.0ma output low all output pins v ol 0.4 v i ol = 1.6ma voltage ports 1 and 2 1.0 v i ol = 10.0ma input leakage res |i in | 10.0 a v in = 0.5v to current stby, nmi, 1.0 a v cc ?0.5v md 1 , md 0 p7 7 ?p7 0 1.0 a v in = 0.5v to av cc ?0.5v leakage current ports 1, 2, 3 |i tsi | 1.0 a v in = 0.5v to in 3-state (off state) 4, 5, 6, 8, 9 v cc ?0.5v input pull-up ports 1, 2, 3 -ip 30 250 a v in = 0v mos current 4, 5, 6, 8, 9 * connect av cc to the power supply (+5v) even when the a/d converter is not used. 270 table 17-2. dc characteristics (cont.) conditions: v cc = av cc = 5.0v 10%, v ss = av ss = 0v, ta = ?0 to 75?c (regular specifications) ta = ?0 to 85?c (wide-range specifications) measurement item symbol min typ max unit conditions input capacitance res (v pp ) c in 60 pf v in = 0v nmi 30 pf all input pins 15 pf f = 1mhz except res ta = 25?c and nmi current normal i cc 12 25 m a f = 6mhz dissipation *1 operation 16 30 m a f = 8mhz 20 40 m a f = 10mhz sleep mode 8 15 m a f = 6mhz 10 20 m a f = 8mhz 12 25 m a f = 10mhz standby modes *2 0.01 5.0 a analog supply during a/d ai cc 0.6 1.5 m a current conversion waiting 0.01 5.0 a ram standby v ram 2.0 v voltage *1 current dissipation values assume that v ih min. = v cc ?0.5v, v il max. = 0.5v, all output pins are in the no-load state, and all mos input pull-ups are off. *2 for these values it is assumed that v ram v cc < 4.5v and v ih min. = v cc 0.9, v il max. = 0.3v. 271 table 17-3. allowable output current sink values conditions: v cc = av cc = 5.0v 10%, v ss = av ss = 0v, ta = ?0 to 75?c (regular specifications) ta = ?0 to 85?c (wide-range specifications) item symbol min typ max unit allowable output low ports 1 and 2 i ol 10 ma current sink (per pin) other output pins 2.0 ma allowable output low ports 1 and 2, total s i ol 80 ma current sink (total) all output pins 120 ma allowable output high all output pins ? oh 2.0 ma current sink (per pin) allowable output high total of all output s ? oh 40 ma current sink (total) note: to avoid degrading the reliability of the chip, be careful not to exceed the output current sink values in table 17-3. in particular, when driving a darlington transistor pair or led directly, be sure to insert a current-limiting resistor in the output path. see figures 17-1 and 17-2. figure 17-1. example of circuit for driving a darlington pair figure 17-2. example of circuit for driving a led h8/330 port 2 k darlington pair vcc 600 led port 1 or 2 h8/330 272 17.2.2 ac characteristics the ac characteristics of the h8/330 chip are listed in three tables. bus timing parameters are given in table 17-4, control signal timing parameters in table 17-5, and timing parameters of the on- chip supporting modules in table 17-6. table 17-4. bus timing conditions: v cc = 5.0v 10%, = 0.5 to 10mhz, v ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) measurement measurement 6mhz 8mhz 10mhz item symbol conditions min max min max min max unit clock cycle time t cyc fig. 17-4 166.7 2000 125 2000 100 2000 ns clock pulse width low t cl fig. 17-4 65 45 35 ns clock pulse width high t ch fig. 17-4 65 45 35 ns clock rise time t cr fig. 17-4 15 15 15 ns clock fall time t cf fig. 17-4 15 15 15 ns address delay time t ad fig. 17-4 70 60 55 ns address hold time t ah fig. 17-4 30 25 20 ns address strobe delay time t asd fig. 17-4 70 60 50 ns write strobe delay time t wsd fig. 17-4 70 60 50 ns strobe delay time t sd fig. 17-4 70 60 50 ns write strobe pulse width t wsw fig. 17-4 200 150 120 ns address setup time 1 t as1 fig. 17-4 25 20 15 ns address setup time 2 t as2 fig. 17-4 105 80 65 ns read data setup time t rds fig. 17-4 70 55 50 ns read data hold time t rdh fig. 17-4 0 0 0 ns write data delay time t wdd fig. 17-4 70 60 60 ns read data access time t acc fig. 17-4 270 190 160 ns write data setup time t wds fig. 17-4 30 15 10 ns write data hold time t wdh fig. 17-4 30 25 20 ns wait setup time t wts fig. 17-5 40 40 40 ns wait hold time t wth fig. 17-5 10 10 10 ns e clock delay time t ed fig. 17-6 20 20 20 ns e clock rise time t er fig. 17-6 15 15 15 ns e clock fall time t ef fig. 17-6 15 15 15 ns read data hold time t rdhe fig. 17-6 0 0 0 ns (for e clock) write data hold time t wdhe fig. 17-6 50 40 30 ns (for e clock) 273 table 17-5. control signal timing conditions: v cc = 5.0v 10%, = 0.5 to 10mhz, v ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) measurement measurement 6mhz 8mhz 10mhz item symbol conditions min max min max min max unit res setup time t ress fig. 17-7 200 200 200 ns res pulse width t resw fig. 17-7 10 10 10 t cyc mode programming t mds fig. 17-7 4 4 4 t cyc setup time nmi setup time t nmis fig. 17-8 110 110 110 ns (nmi, irq 0 to irq 7 ) nmi hold time t nmih fig. 17-8 10 10 10 ns (nmi, irq 0 to irq 7 ) interrupt pulse width t nmiw fig. 17-8 200 200 200 ns for recovery from soft- ware standby mode (nmi, irq 0 to irq 2 ) crystal oscillator settling t osc1 fig. 17-9 20 20 20 ms time (reset) crystal oscillator settling t osc2 fig. 17-10 10 10 10 ms time (software standby) table 17-6. timing conditions of on-chip supporting modules conditions: v cc = 5.0v 10%, = 0.5 to 10mhz, v ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) measurement 6mhz 8mhz 10mhz item symbol conditions min max min max min max unit frt timer output t ftod fig. 17-11 100 100 100 ns delay time timer input t ftis fig. 17-11 50 50 50 ns setup time timer clock t ftcs fig. 17-12 50 50 50 ns input setup time timer clock t ftcwh fig. 17-12 1.5 1.5 1.5 t cyc pulse width t ftcwl 274 table 17-6. timing conditions of on-chip supporting modules (cont.) conditions: v cc = 5.0v 10%, = 0.5 to 10mhz, v ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) measurement 6mhz 8mhz 10mhz item symbol conditions min max min max min max unit tmr timer output t tmod fig. 17-13 100 100 100 ns delay time timer reset t tmrs fig. 17-15 50 50 50 ns input setup time timer clock t tmcs fig. 17-14 50 50 50 ns input setup time timer clock t tmcwh fig. 17-14 1.5 1.5 1.5 t cyc pulse width (single edge) timer clock t tmcwl fig. 17-14 2.5 2.5 2.5 t cyc pulse width (both edges) pwm timer output t pwod fig. 17-16 100 100 100 ns delay time sci input (async) t scyc fig. 17-17 2 2 2 t cyc clock (sync) t scyc fig. 17-17 4 4 4 t cyc cycle transmit data t txd fig. 17-17 100 100 100 ns delay time (sync) receive data t rxs fig. 17-17 100 100 100 ns setup time (sync) receive data t rxh fig. 17-17 100 100 100 ns hold time (sync) input clock t sckw fig. 17-18 0.4 0.6 0.4 0.6 0.4 0.6 t scyc pulse width ports output data t pwd fig. 17-19 100 100 100 ns delay time input data setup t prs fig. 17-19 50 50 50 ns time input data hold t prh fig. 17-19 50 50 50 ns time 275 table 17-6. timing conditions of on-chip supporting modules (cont.) conditions: v cc = 5.0v 10%, = 0.5 to 10mhz, v ss = 0v, ta = ?0 to 75?c (regular specifications), ta = ?0 to 85?c (wide-range specifications) measurement 6mhz 8mhz 10mhz item symbol conditions min max min max min max unit dual- address t daa fig. 17-20 150 150 150 ns port access time ram cs access t dacs fig. 17-20 130 130 130 ns read time cycle oe output t doe fig. 17-20 70 70 70 ns delay time cs output t dchz fig. 17-20 50 50 50 ns floating time oe output t dohz fig. 17-20 50 50 50 ns floating time output data t doh fig. 17-20 0 0 0 ns hold time dual- chip select time t dcw fig. 17-21 100 100 100 ns port address valid t daw fig. 17-21 100 100 100 ns ram time write address setup t das fig. 17-21 20 20 20 ns cycle time write pulse t dwp fig. 17-21 90 90 90 ns width address hold t dwr fig. 17-21 20 20 20 ns time input data t ddw fig. 17-21 60 60 60 ns setup time input data t ddh fig. 17-21 15 15 15 ns hold time 276 ? measurement conditions for ac characteristics figure 17-3. output load circuit 17.2.3 a/d converter characteristics table 17-7 lists the characteristics of the on-chip a/d converter. table 17-7. a/d converter characteristics conditions: v cc = av cc = 5.0v 10%, v ss = av ss = 0v, ta = ?0 to 75?c (regular specifications) ta = ?0 to 85?c (wide-range specifications) fig. 17-3 5 v lsi output pin input/output timing reference levels low: high: 0.8 v 2.0 v 90 pf: ports 1 ?4, 6, 9 30 pf: ports 5, 8 2.4 k 12 k c = r l = r h = c r l r h 6mhz 8mhz 10mhz item min typ max min typ max min typ max unit resolution 8 8 8 8 8 8 8 8 8 bits conversion time 20.4 15.25 12.2 s (single mode) analog input capacitance 20 20 20 pf allowable signal 10 10 10 k source impedance nonlinearity error 1 1 1 lsb offset error 1 1 1 lsb full-scale error 1 1 1 lsb quantizing error 0.5 0.5 0.5 lsb absolute accuracy 1.5 1.5 1.5 lsb 277 17.3 mcu operational timing this section provides the following timing charts: 17.3.1 bus timing figures 17-4 to 17-6 17.3.2 control signal timing figures 17-7 to 17-10 17.3.3 16-bit free-running timer timing figures 17-11 to 17-12 17.3.4 8-bit timer timing figures 17-13 to 17-15 17.3.5 pwm timer timing figure 17-16 17.3.6 sci timing figures 17-17 to 17-18 17.3.7 i/o port timing figure 17-19 17.3.8 dual-port ram timing figures 17-20 to 17-21 17.3.1 bus timing (1) basic bus cycle (without wait states) in expanded modes figure 17-4. basic bus cycle (without wait states) in expanded modes t t 1 t cyc 2 t 3 t ch t cl t ad t cr t asd t acc t rds t wsd t as2 t wdd t wds t wdh t ah t wsw t rdh t ah t sd a 15 to a 0 ios wr d 7 to d 0 (read) d 7 to d 0 (write) as, rd (read) t cf t asi t sd fig. 17-4 278 (2) basic bus cycle (with 1 wait state) in expanded modes figure 17-5. basic bus cycle (with 1 wait state) in expanded modes as, rd wr wait d 7 to d 0 (read) a 15 to a 0 ios d 7 to d 0 (write) t 1 t 2 t w t 3 t wts t wth t wts t wth 279 (3) e clock bus cycle figure 17-6. e clock bus cycle 17.3.2 control signal timing (1) reset input timing figure 17-7. reset input timing t ad t ed t e r t e f t ed t ah t sd t as1 t ad t rds t rdh t rdhe t wdhe e a 15 ?a 0 , ios as rd, wr d 7 to d 0 (read) d 7 to d 0 (write) t ad fig. 17-6 md 1 and md 0 res t ress t mds t ress t resw 280 (2) interrupt input timing figure 17-8. interrupt input timing irq i (level) nmi irq i t t t nmi irq i (edge) nmis nmis nmih t nmiw note : i = 0 to 7 fig. 17-8 281 (3) clock settling timing v cc res stby t osc1 t osc1 figure 17-9. clock settli ng timing 282 (4) clock settling timing for recovery from software standby mode figure 17-10. clock settling timing for recovery from software standby mode 17.3.3 16-bit free-running timer timing (1) free-running timer input/output timing figure 17-11. free-running timer input/output timing osc2 nmi irq i (i = 0, 1, 2) t compare-match ftia, ftib, ftic, ftid ftoa , ftob free-running timer counter t ftod t ftis 283 (2) external clock input timing for free-running timer figure 17-12. external clock input timing for free-running timer 17.3.4 8-bit timer timing (1) 8-bit timer output timing figure 17-13. 8-bit timer output timing (2) 8-bit timer clock input timing figure 17-14. 8-bit timer clock input timing ftci t ftcs t ftcwl t ftcwh timer counter compare- match tmci 1 , tmci 0 t tmod t tmcs t tmcs t tmcwl t tmcwh tmci 0 , tmci 1 284 (3) 8-bit timer reset input timing figure 17-15. 8-bit timer reset input timing 17.3.5 pulse width modulation timer timing figure 17-16. pwm timer output timing 17.3.6 serial communication interface timing (1) sci input/output timing figure 17-17. sci input/output timing (synchronous mode) n h'00 timer counter t tmrs tmri 0 , tmri 1 compare- match t pwod timer counter pw 0 , pw 1 t scyc t txd t rxs t rxh serial clock (csck) transmit data (ctxd) receive data (crxd) 285 (2) sci input clock timing figure 17-18. sci input clock timing 17.3.7 i/o port timing figure 17-19. i/o port input/output timing t sckw t scyc asck, csck * except p9 6 and p7 7 to p7 0 port read/write cycle t 1 t 2 t 3 t prs t prh t pwd port 1 to port 9 (input) port 1* to port 9 (output) * except p9 6 and p7 7 to p7 0 286 17.3.8 dual-port ram timing (1) read cycle 1 (2) read cycle 2 (3) read cycle 3 figure 17-20. dual-port ram read timing t daa t doe t dacs t doh t dohz t dchz rs 3 to rs 0 ddb 7 to ddb 0 oe cs note: we should be high during a read cycle. t daa rs 3 to rs 0 ddb 7 to ddb 0 t t doh doh notes: 1. we should be high during a read cycle. 2. cs = v il 3. oe = v il ddb 7 to ddb 0 t dacs t dchz cs notes: 1. we should be high during a read cycle. 2. the address on the register select lines should be set up by the time cs goes low, or before that time. 3. oe = v il 287 (4) write cycle figure 17-21. dual-port ram write timing rs 3 to rs 0 oe ddb 7 to ddb 0 cs we t dwr 2* t daw t ddw t ddh t das t dcw 3* t dwp 1* notes: 1. data are written while cs and we are both low (t dwp ). 2. t dwr is measured from the rise of cs or we, whichever rises first. 3. if cs goes low at the same time as we goes low or after we goes low, the output remains in the high- impedance state. 288 appendix a. cpu instruction set a.1 instruction set list operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) (ead) destination operand (eas) source operand ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx:3/8/16 immediate data (3, 8, or 16 bits) d:8/16 displacement (8 or 16 bits) @aa:8/16 absolute address (8 or 16 bits) + addition subtraction multiplication division and logical or logical ? exclusive or logical ? move not condition code notation modified according to the instruction result * undetermined (unpredictable) 0 always cleared to "0" not affected by the instruction result 289 290 mov.b #xx:8,rd b #xx:8 ? rd8 2 C C 0 C 2 mov.b rs,rd b rs8 ? rd8 2 C C 0 C 2 mov.b @rs,rd b @rs16 ? rd8 2 C C 0 C 4 mov.b @(d:16,rs),rd b @(d:16,rs16) ? rd8 4 C C 0 C 6 mov.b @rs+,rd b @rs16 ? rd8 2 C C 0 C 6 rs16+1 ? rs16 mov.b @aa:8,rd b @aa:8 ? rd8 2 C C 0 C 4 mov.b @aa:16,rd b @aa:16 ? rd8 4 C C 0 C 6 mov.b rs,@rd b rs8 ? @rd16 2 C C 0 C 4 mov.b rs,@(d:16,rd) b rs8 ? @(d:16,rd16) 4 C C 0 C 6 mov.b rs,@Crd b rd16C1 ? rd16 2 C C 0 C 6 rs8 ? @rd16 mov.b rs,@aa:8 b rs8 ? @aa:8 2 C C 0 C 4 mov.b rs,@aa:16 b rs8 ? @aa:16 4 C C 0 C 6 mov.w #xx:16,rd w #xx:16 ? rd 4 C C 0 C 4 mov.w rs,rd w rs16 ? rd16 2 C C 0 C 2 mov.w @rs,rd w @rs16 ? rd16 2 C C 0 C 4 mov.w @(d:16,rs),rd w @(d:16,rs16) ? rd16 4 C C 0 C 6 mov.w @rs+,rd w @rs16 ? rd16 2 C C 0 C 6 rs16+2 ? rs16 mov.w @aa:16,rd w @aa:16 ? rd16 4 C C 0 C 6 mov.w rs,@rd w rs16 ? @rd16 2 C C 0 C 4 mov.w rs,@(d:16,rd) w rs16 ? @(d:16,rd16) 4 C C 0 C 6 mov.w rs,@Crd w rd16C2 ? rd16 2 C C 0 C 6 rs16 ? @rd16 mov.w rs, @aa:16 w rs16 ? @aa:16 4 C C 0 C 6 pop rd w @sp ? rd16 2 C C 0 C 6 sp+2 ? sp push rs w spC2 ? sp 2 C C 0 C 6 rs16 ? @sp movfpe @aa:16,rd b not supported movtpe rs,@aa:16 b not supported eepmov C if r4l 1 0 then 4 C C C C C C ? repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4lC1 ? r4l until r4l=0 else next appendix b. instruction set list i h n z v c mnemonic operation condition code addressing mode/ instruction length s i z e # x x : 8 / 1 6 r n @ r n @(d:16, rn) @ - r n / @ r n + @ a a : 8 / 1 6 @(d:8, pc) @ @ a a implied no. of states* 291 add.b #xx:8,rd b rd8+#xx:8 ? rd8 2 C 2 add.b rs,rd b rd8+rs8 ? rd8 2 C 2 add.w rs,rd w rd16+rs16 ? rd16 2 C ? 2 addx.b #xx:8,rd b rd8+#xx:8 +c ? rd8 2 C 2 addx.b rs,rd b rd8+rs8 +c ? rd8 2 C 2 adds.w #1,rd w rd16+1 ? rd16 2 C C C C C C 2 adds.w #2,rd w rd16+2 ? rd16 2 C C C C C C 2 inc.b rd b rd8+1 ? rd8 2 C C C 2 daa.b rd b rd8 decimal adjust ? rd8 2 C * * ? 2 sub.b rs,rd b rd8Crs8 ? rd8 2 C 2 sub.w rs,rd w rd16Crs16 ? rd16 2 C ? 2 subx.b #xx:8,rd b rd8C#xx:8 Cc ? rd8 2 C 2 subx.b rs,rd b rd8Crs8 Cc ? rd8 2 C 2 subs.w #1,rd w rd16C1 ? rd16 2 C C C C C C 2 subs.w #2,rd w rd16C2 ? rd16 2 C C C C C C 2 dec.b rd b rd8C1 ? rd8 2 C C C 2 das.b rd b rd8 decimal adjust ? rd8 2 C * * C 2 neg.b rd b 0Crd ? rd 2 C 2 cmp.b #xx:8,rd b rd8C#xx:8 2 C 2 cmp.b rs,rd b rd8Crs8 2 C 2 cmp.w rs,rd w rd16Crs16 2 C ? 2 mulxu.b rs,rd b rd8 rs8 ? rd16 2 C C C C C C 14 divxu.b rs,rd b rd16 ? rs8 ? rd16 2 C C ? d C C 14 (rdh:remainder, rdl:quotient) and.b #xx:8,rd b rd8 #xx:8 ? rd8 2 C C 0 C 2 and.b rs,rd b rd8 rs8 ? rd8 2 C C 0 C 2 or.b #xx:8,rd b rd8 #xx:8 ? rd8 2 C C 0 C 2 or.b rs,rd b rd8 rs8 ? rd8 2 C C 0 C 2 xor.b #xx:8,rd b rd8 ? #xx:8 ? rd8 2 C C 0 C 2 xor.b rs,rd b rd8 ? rs8 ? rd8 2 C C 0 C 2 not.b rd b rd ? rd 2 C C 0 C 2 i h n z v c addressing mode/ instruction length appendix b. instruction set list (cont.) mnemonic operation condition code s i z e no. of states* # x x : 8 / 1 6 r n @ r n @(d:16, rn) @ - r n / @ r n + @ a a : 8 / 1 6 @(d:8, pc) @ @ a a 292 c shal.b rd b 2 C C 2 shar.b rd b 2 C C 0 2 shll.b rd b 2 C C 0 2 shlr.b rd b 2 C C 0 0 2 rotxl.b rd b 2 C C 0 2 rotxr.b rd b 2 C C 0 2 rotl.b rd b 2 C C 0 2 rotr.b rd b 2 C C 0 2 bset #xx:3,rd b (#xx:3 of rd8) ? 1 2 C C C C C C 2 bset #xx:3,@rd b (#xx:3 of @rd16) ? 1 4 C C C C C C 8 bset #xx:3,@aa:8 b (#xx:3 of @aa:8) ? 1 4 C C C C C C 8 bset rn,rd b (rn8 of rd8) ? 1 2 C C C C C C 2 bset rn,@rd b (rn8 of @rd16) ? 1 4 C C C C C C 8 bset rn,@aa:8 b (rn8 of @aa:8) ? 1 4 C C C C C C 8 bclr #xx:3,rd b (#xx:3 of rd8) ? 0 2 C C C C C C 2 bclr #xx:3,@rd b (#xx:3 of @rd16) ? 0 4 C C C C C C 8 bclr #xx:3,@aa:8 b (#xx:3 of @aa:8) ? 0 4 C C C C C C 8 bclr rn,rd b (rn8 of rd8) ? 0 2 C C C C C C 2 bclr rn,@rd b (rn8 of @rd16) ? 0 4 C C C C C C 8 bclr rn,@aa:8 b (rn8 of @aa:8) ? 0 4 C C C C C C 8 bnot #xx:3,rd b (#xx:3 of rd8) ? (#xx:3 of rd8) 2 C C C C C C 2 bnot #xx:3,@rd b (#xx:3 of @rd16) ? (#xx:3 of @rd16) 4 C C C C C C 8 bnot #xx:3,@aa:8 b (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) 4 C C C C C C 8 c 0 i h n z v c 0 c 0 c c 0 c 0 c c b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 b 0 b 7 addressing mode/ instruction length mnemonic operation condition code appendix b. instruction set list (cont.) # x x : 8 / 1 6 s i z e r n @ r n @(d:16, rn) @ - r n / @ r n + @ a a : 8 / 1 6 @(d:8, pc) @ @ a a no. of states* 293 bnot rn,rd b (rn8 of rd8) ? (rn8 of rd8) 2 C C C C C C 2 bnot rn,@rd b (rn8 of @rd16) ? (rn8 of @rd16) 4 C C C C C C 8 bnot rn,@aa:8 b (rn8 of @aa:8) ? (rn8 of @aa:8) 4 C C C C C C 8 btst #xx:3,rd b (#xx:3 of rd8) ? z 2 C C C C C 2 btst #xx:3,@rd b (#xx:3 of @rd16) ? z 4 C C C C C 6 btst #xx:3,@aa:8 b (#xx:3 of @aa:8) ? z 4 C C C C C 6 btst rn,rd b (rn8 of rd8) ? z 2 C C C C C 2 btst rn,@rd b (rn8 of @rd16) ? z 4 C C C C C 6 btst rn,@aa:8 b (rn8 of @aa:8) ? z 4 C C C C C 6 bld #xx:3,rd b (#xx:3 of rd8) ? c 2 C C C C C 2 bld #xx:3,@rd b (#xx:3 of @rd16) ? c 4 C C C C C 6 bld #xx:3,@aa:8 b (#xx:3 of @aa:8) ? c 4 C C C C C 6 bild #xx:3,rd b (#xx:3 of rd8) ? c 2 C C C C C 2 bild #xx:3,@rd b (#xx:3 of @rd16) ? c 4 C C C C C 6 bild #xx:3,@aa:8 b (#xx:3 of @aa:8) ? c 4 C C C C C 6 bst #xx:3,rd b c ? (#xx:3 of rd8) 2 C C C C C C 2 bst #xx:3,@rd b c ? (#xx:3 of @rd16) 4 C C C C C C 8 bst #xx:3,@aa:8 b c ? (#xx:3 of @aa:8) 4 C C C C C C 8 bist #xx:3,rd b c ? (#xx:3 of rd8) 2 C C C C C C 2 bist #xx:3,@rd b c ? (#xx:3 of @rd16) 4 C C C C C C 8 bist #xx:3,@aa:8 b c ? (#xx:3 of @aa:8) 4 C C C C C C 8 band #xx:3,rd b c (#xx:3 of rd8) ? c 2 C C C C C 2 band #xx:3,@rd b c (#xx:3 of @rd16) ? c 4 C C C C C 6 band #xx:3,@aa:8 b c (#xx:3 of @aa:8) ? c 4 C C C C C 6 biand #xx:3,rd b c (#xx:3 of rd8) ? c 2 C C C C C 2 biand #xx:3,@rd b c (#xx:3 of @rd16) ? c 4 C C C C C 6 biand #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 C C C C C 6 bor #xx:3,rd b c (#xx:3 of rd8) ? c 2 C C C C C 2 bor #xx:3,@rd b c (#xx:3 of @rd16) ? c 4 C C C C C 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 C C C C C 6 bior #xx:3, rd b c (#xx:3 of rd8) ? c 2 C C C C C 2 addressing mode/ instruction length mnemonic operation condition code i h n z v c appendix b. instruction set list (cont.) s i z e # x x : 8 / 1 6 r n @ r n @(d:16, rn) @ - r n / @ r n + @ a a : 8 / 1 6 @(d:8, pc) @ @ a a no. of states* 294 bior #xx:3,@rd b c (#xx:3 of @rd16) ? c 4 C C C C C 6 bior #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 C C C C C 6 bxor #xx:3,rd b c ? (#xx:3 of rd8) ? c 2 C C C C C 2 bxor #xx:3,@rd b c ? (#xx:3 of @rd16) ? c 4 C C C C C 6 bxor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 C C C C C 6 bixor #xx:3,rd b c ? (#xx:3 of rd8) ? c 2 C C C C C 2 bixor #xx:3,@rd b c ? (#xx:3 of @rd16) ? c 4 C C C C C 6 bixor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 C C C C C 6 bra d:8 (bt d:8) C pc ? pc+d:8 2 C C C C C C 4 brn d:8 (bf d:8) C pc ? pc+2 2 C C C C C C 4 bhi d:8 C if condition c z = 0 2 C C C C C C 4 bls d:8 C is true then c z = 1 2 C C C C C C 4 bcc d:8 (bhs d:8) C pc ? pc+d:8 c = 0 2 C C C C C C 4 bcs d:8 (blo d:8) C else next; c = 1 2 C C C C C C 4 bne d:8 C z = 0 2 C C C C C C 4 beq d:8 C z = 1 2 C C C C C C 4 bvc d:8 C v = 0 2 C C C C C C 4 bvs d:8 C v = 1 2 C C C C C C 4 bpl d:8 C n = 0 2 C C C C C C 4 bmi d:8 C n = 1 2 C C C C C C 4 bge d:8 C n ? v = 0 2 C C C C C C 4 blt d:8 C n ? v = 1 2 C C C C C C 4 bgt d:8 C z (n ? v) = 0 2 C C C C C C 4 ble d:8 C z (n ? v) = 1 2 C C C C C C 4 jmp @rn C pc ? rn16 2 C C C C C C 4 jmp @aa:16 C pc ? aa:16 4 C C C C C C 6 jmp @@aa:8 C pc ? @aa:8 2 C C C C C C 8 bsr d:8 C spC2 ? sp 2 C C C C C C 6 pc ? @sp pc ? pc+d:8 i h n z v c addressing mode/ instruction length mnemonic operation condition code branching condition appendix b. instruction set list (cont.) s i z e # x x : 8 / 1 6 r n @ r n @(d:16, rn) @ - r n / @ r n + @ a a : 8 / 1 6 @(d:8, pc) @ @ a a no. of states* 295 jsr @rn C spC2 ? sp 2 C C C C C C 6 pc ? @sp pc ? rn16 jsr @aa:16 C spC2 ? sp 4 C C C C C C 8 pc ? @sp pc ? aa:16 jsr @@aa:8 spC2 ? sp 2 C C C C C C 8 pc ? @sp pc ? @aa:8 rts C pc ? @sp 2 C C C C C C 8 sp+2 ? sp rte C ccr ? @sp 2 10 sp+2 ? sp pc ? @sp sp+2 ? sp sleep C transit to sleep mode. 2 C C C C C C 2 ldc #xx:8,ccr b #xx:8 ? ccr 2 2 ldc rs,ccr b rs8 ? ccr 2 2 stc ccr,rd b ccr ? rd8 2 C C C C C C 2 andc #xx:8,ccr b ccr #xx:8 ? ccr 2 2 orc #xx:8,ccr b ccr #xx:8 ? ccr 2 2 xorc #xx:8,ccr b ccr ? #xx:8 ? ccr 2 2 nop C pc ? pc+2 2 C C C C C C 2 notes: the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. 1 if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. ? set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. ? the number of states required for execution is 4n+8 (n = value of r4l) these instructions are not supported by the h8/338 series. set to 1 if the divisor is negative; otherwise cleared to 0. cleared to 0 if the divisor is not zero; undetermined when the divisor is zero. i h n z v c addressing mode/ instruction length mnemonic operation condition code appendix b. instruction set list (cont.) s i z e @ - r n / @ r n + @ a a : 8 / 1 6 # x x : 8 / 1 6 r n @ r n @(d:16, rn) @(d:8, pc) @ @ a a implied no. of states* a.2 operation code map table a-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). some pairs of instructions have identical first bytes. these instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is "0." instruction when first bit of byte 2 (bit 7 of first instruction word) is "1." 296 table a-2. operation code map * 1 the movfpe and movtpe instructions are identical to mov instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word). the push and pop instructions are identical in machine language to mov instructions. * 2 the bt, bf, bhs, and blo instructions are identical in machine language to bra, brn, bcc, and bcs, respectively. hi lo 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f nop sleep stc ldc orc xorc andc ldc add inc adds mov addx daa shll shal shlr shar rotxl rotl rotxr rotr not neg or xor and sub dec subs cmp subx das mov bra brn bhi bls bcc bcs bne beq bvs bpl bmi blt bgt ble mulxu divxu rts bsr rte jmp jsr bvc bge bset bnot bclr btst mov mov eepmov add addx cmp subx or xor and mov bxor bixor band biand bor bior bld bild bst bist bit manipulation instruction *1 *2 *2 *2 *2 297 a.3 number of states required for execution the tables below can be used to calculate the number of states required for instruction execution. table a-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). table a-4 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: mode 1 (on-chip rom disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. bset #0, @ffc7 from table a-4: i = l = 2, j = k = m = n= 0 from table a-3: s i = 8, s l = 3 number of states required for execution: 2 8 + 2 3 =22 2. jsr @@30 from table a-4: i = 2, j = k = 1, l = m = n = 0 from table a-3: s i = s j = s k = 8 number of states required for execution: 2 8 + 1 8 + 1 8 = 32 table a-3. number of states taken by each cycle in instruction execution execution status access location (instruction cycle) on-chip memory on-chip reg. field external memory instruction fetch s i branch address read s j 6 6 + 2m stack operation s k 2 byte data access s l 3 3 + m word data access s m 6 6 + 2m internal operation s n 2 notes: 1. m: number of wait states inserted in access to external device. 2. the byte data access cycle to an external device by the movfpe and movtpe instructions requires 9 to 16 states since it is synchronized with the e clock. see section 15, "e-clock interface" for timing details. 298 table a-4. number of cycles in each instruction instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1/2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 299 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3 rd 1 bior #xx:3 @rd 2 1 bior #xx:3 @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 bset rn, @aa:8 2 2 300 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp.b #xx:8, rd 1 cmp.b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 6 eepmov eepmov 2 2n+2 *1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 1 jmp @@aa:8 2 1 1 jsr jsr @rn 2 1 jsr @aa:16 2 1 1 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 mov.b @(d:16,rs), rd 2 1 301 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n mov mov.b @rs+, rd 1 1 1 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 2 1 mov.b rs, @?d 1 1 1 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 2 1 mov.w @rs+, rd 1 1 1 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 2 1 mov.w rs, @?d 1 1 1 mov.w rs, @aa:16 2 1 movfpe movfpe @aa:16, rd 2 1 *2 movtpe movtpe. rs, @aa:16 2 1 *2 mulxu mulxu. rs, rd 1 6 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 1 rts rts 2 1 1 302 table a-4. number of cycles in each instruction (cont.) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr , rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1/2, rd 1 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 notes: *1 n: initial value in r4l. source and destination are accessed n + 1 times each. *2 data access requires 9 to 16 states. 303 appendix b. register field b.1 register addresses and bit names addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'80 external h'81 addresses h'82 (in h'83 expanded h'84 modes) h'85 h'86 h'87 h'88 h'89 h'8a h'8b h'8c h'8d h'8e h'8f h?0 tier iciae icibe icice icide ociae ocibe ovie frt h?1 tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra h?2 frc (h) h?3 frc (l) h?4 ocra (h) ocrb (h) h?5 ocra (l) ocrb (l) h?6 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h?7 tocr ocrs oea oeb olvla olvlb h?8 icra (h) h?9 icra (l) h?a icrb (h) h?b icrb (l) h?c icrc (h) h?d icrc (l) h?e icrd (h) h?f icrd (l) notes: frt: free-running timer (continued on next page) 304 (continued from previous page) addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h?0 tcr oe os cks2 cks1 cks0 pwm0 h?1 dtr h?2 tcnt h?3 h?4 tcr oe os cks2 cks1 cks0 pwm1 h?5 dtr h?6 tcnt h?7 h'a8 external h'a9 addresses h'aa (in h'ab expanded h'ac modes) h'ad h'ae h'af h?0 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddrp1 1 ddr p1 0 ddr port 1 h?1 p2ddr p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddrp2 1 ddr p2 0 ddr port 2 h?2 p1dr p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h?3 p2dr p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h?4 p3ddr p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddrp3 1 ddr p3 0 ddr port 3 h?5 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddrp4 1 ddr p4 0 ddr port 4 h?6 p3dr p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 h?7 p4dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h?8 p5ddr p5 2 ddrp5 1 ddr p5 0 ddr port 5 h?9 p6ddr p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddrp6 1 ddr p6 0 ddr port 6 h?a p5dr p5 2 p5 1 p5 0 port 5 h?b p6dr p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h?c h?d p8ddr p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddrp8 1 ddr p8 0 ddr port 8 h?e p7dr p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h?f p8dr p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 port 8 (continued on next page) notes: pwm0: pulse-width modulation timer channel 0 pwm1: pulse-width modulation timer channel 1 305 (continued from preceding page) addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h?0 p9ddr p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddrp9 1 ddr p9 0 ddr port 9 h?1 p9dr p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 h?2 h?3 h?4 syscr ssby sts2 sts1 sts0 nmieg dpme rame system h?5 mdcr mds1 mds0 control h?6 iscr irq 7 sc irq 6 sc irq 5 sc irq 4 sc irq 3 sc irq 2 sc irq 1 sc irq 0 sc h?7 ier irq 7 e irq 6 e irq 5 e irq 4 e irq 3 e irq 2 e irq 1 e irq 0 e h?8 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr0 h?9 tcsr cmfb cmfa ovf os3 os2 os1 os0 h?a tcora h?b tcorb h?c tcnt h?d h?e h?f h?0 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr1 h?1 tcsr cmfb cmfa ovf os3 os2 os1 os0 h?2 tcora h?3 tcorb h?4 tcnt h?5 h?6 h?7 h?8 smr c/a chr pe o/e stop cks1 cks0 sci h?9 brr h?a scr tie rie te re cke1 cke0 h?b tdr h?c ssr tdre rdrf orer fer per h?d rdr h?e h?f (continued on next page) notes: tmr0: 8-bit timer channel 0 tmr1: 8-bit timer channel 1 sci: serial communication interface 306 (continued from preceding page) addr. (last register bit names byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h?0 addra a/d h?1 h?2 addrb h?3 h?4 addrc h?5 h?6 addrd h?7 h?8 adcsr adf adie adst scan cks ch2 ch1 ch0 h?9 h?a adcr trge h?b h?c h?d h?e h?f h?0 pccsr mwef emwi swef eakar mref emri mwmf swmf dpram h?1 pcdr0 h?2 pcdr1 h?3 pcdr2 h?4 pcdr3 h?5 pcdr4 h?6 pcdr5 h?7 pcdr6 h?8 pcdr7 h?9 pcdr8 h?a pcdr9 h?b pcdr10 h?c pcdr11 h?d pcdr12 h?e pcdr13 h?f pcdr14 note: a/d: analog-to-digital converter dpram: dual-port ram 307 308 tier?imer interrupt enable register h?f90 frt bit 7 6 5 4 3 2 1 0 iciae icibe icice icide ociae ocibe ovie initial value 0 0 0 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w overflow interrupt enable 0 overflow interrupt request is disabled. 1 overflow interrupt request is enabled. output compare interrupt b enable 0 output compare interrupt request b is disabled. 1 output compare interrupt request b is enabled. output compare interrupt a enable 0 output compare interrupt request a is disabled. 1 output compare interrupt request a is enabled. input capture interrupt d enable 0 input capture interrupt request d is disabled. 1 input capture interrupt request d is enabled. input capture interrupt c enable 0 input capture interrupt request c is disabled. 1 input capture interrupt request c is enabled. input capture interrupt b enable 0 input capture interrupt request b is disabled. 1 input capture interrupt request b is enabled. input capture interrupt a enable 0 input capture interrupt request a is disabled. 1 input capture interrupt request a is enabled. 309 tcsr?imer control/status register h?f91 frt bit 7 6 5 4 3 2 1 0 icfa icfb icfc icfd ocfa ocfb ovf cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* r/w counter clear a 0 frc count is not cleared. 1 frc count is cleared by compare-match a. timer overflow flag 0 cleared when cpu reads ovf = ?,?then writes ??in ovf. 1 set when frc changes from h?fff to h?000. output compare flag b 0 cleared when cpu reads ocfb = ?? then writes ??in ocfb. 1 set when frc = ocrb. output compare flag a 0 cleared when cpu reads ocfa = ?? then writes ??in ocfa. 1 set when frc = ocra. input capture flag d 0 cleared when cpu reads icfd = ?? then writes ??in icfd. 1 set by ftid input. input capture flag c 0 cleared when cpu reads icfc = ?? then writes ??in icfc. 1 set by ftic input. input capture flag b 0 cleared when cpu reads icfb = ?? then writes ??in icfb. 1 set when ftib input causes frc to be copied to icrb. input capture flag a 0 cleared when cpu reads icfa = ?? then writes ??in icfa. 1 set when ftia input causes frc to be copied to icra. * software can write a "0" in bits 7 to 1 to clear the flags, but cannot write a "1" in these bits 310 frc (h and l)?ree-running counter h?f92, h?f93 frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value ocra (h and l)?utput compare register a h?f94, h?f95 frt bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w continually compared with frc. ocfa is set to ??when ocra = frc. ocrb (h and l)?utput compare register b h?f94, h?f95 frt bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w continually compared with frc. ocfb is set to ??when ocrb = frc. 311 tcr?imer control register h?f96 frt bit 7 6 5 4 3 2 1 0 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w clock select 0 0 internal clock source: /2 0 1 internal clock source: /8 1 0 internal clock source: /32 1 1 external clock source: counted on rising edge buffer enable b 0 icrd is used for input capture d. 1 icrd is buffer register for input capture b. buffer enable a 0 icrc is used for input capture c. 1 icrc is buffer register for input capture a. input edge select d 0 falling edge of ftid is valid. 1 rising edge of ftid is valid. input edge select c 0 falling edge of ftic is valid. 1 rising edge of ftic is valid. input edge select b 0 falling edge of ftib is valid. 1 rising edge of ftib is valid. input edge select a 0 falling edge of ftia is valid. 1 rising edge of ftia is valid. 312 tocr?imer output control register h?f97 frt bit 7 6 5 4 3 2 1 0 ocrs oea oeb olvla olvlb initial value 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w output level b 0 compare-match b causes ??output. 1 compare-match b causes ??output. output level a 0 compare-match a causes ??output. 1 compare-match a causes ??output. output enable b 0 output compare b output is disabled. 1 output compare b output is enabled. output enable a 0 output compare a output is disabled. 1 output compare a output is enabled. output compare register select 0 the cpu can access ocra at addresses h?f94 ?h?f95. 1 the cpu can access ocrb at addresses h?f94 ?h?f95. icra (h and l)?nput capture register h?f98, h?f99 frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftia input. 313 icrb (h and l)?nput capture register h?f9a, h?f9b frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftib input. icrc (h and l)?nput capture register h?f9c, h?f9d frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftic input, or old icra value in buffer mode. icrd (h and l)?nput capture register h?f9e, h?f9f frt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured on ftid input, or old icrb value in buffer mode. 314 tcr?imer control register h?fa0 pwm0 bit 7 6 5 4 3 2 1 0 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w clock select (values when = 10mhz) internal reso- pwm pwm clock freq. lution period frequency 0 0 0 /2 200ns 50? 20khz 0 0 1 /8 800ns 200? 5khz 0 1 0 /32 3.2? 800? 1.25khz 0 1 1 /128 12.8? 3.2ms 312.5hz 1 0 0 /256 25.6? 6.4ms 156.3hz 1 0 1 /1024 102.4? 25.6ms 39.1hz 1 1 0 /2048 204.8? 51.2ms 19.5hz 1 1 1 /4096 409.6? 102.4ms 9.8hz output select 0 positive logic 1 negative logic output enable 0 pwm output disabled; tcnt cleared to h?0 and stops. 1 pwm output enabled; tcnt runs. dtr?uty register h?fa1 pwm0 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w pulse duty factor 315 tcnt?imer counter h?fa2 pwm0 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value (runs from h?0 to h?9, then repeats from h?0) tcr?imer control register h?fa4 pwm1 bit 7 6 5 4 3 2 1 0 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w note: bit functions are the same as for pwm0. dtr?uty register h?fa5 pwm1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for pwm0. 316 tcnt?imer counter h?fa6 pwm1 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for pwm0. p1ddr?ort 1 data direction register h?fb0 port 1 bit 7 6 5 4 3 2 1 0 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 1 input/output control 0 input port 1 output port p1dr?ort 1 data register h?fb2 port 1 bit 7 6 5 4 3 2 1 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 317 p2ddr?ort 2 data direction register h?fb1 port 2 bit 7 6 5 4 3 2 1 0 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 2 input/output control 0 input port 1 output port p2dr?ort 2 data register h?fb3 port 2 bit 7 6 5 4 3 2 1 0 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3ddr?ort 3 data direction register h?fb4 port 3 bit 7 6 5 4 3 2 1 0 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 3 input/output control 0 input port 1 output port 318 p3dr?ort 3 data register h?fb6 port 3 bit 7 6 5 4 3 2 1 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p4ddr?ort 4 data direction register h?fb5 port 4 bit 7 6 5 4 3 2 1 0 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 4 input/output control 0 input port 1 output port p4dr?ort 4 data register h?fb7 port 4 bit 7 6 5 4 3 2 1 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p5ddr?ort 5 data direction register h?fb8 port 5 bit 7 6 5 4 3 2 1 0 p5 2 ddr p5 1 ddr p5 0 ddr initial value 1 1 1 1 1 0 0 0 read/write w w w port 5 input/output control 0 input port 1 output port 319 p5dr?ort 5 data register h?fba port 5 bit 7 6 5 4 3 2 1 0 p5 2 p5 1 p5 0 initial value 1 1 1 1 1 0 0 0 read/write r/w r/w r/w p6ddr?ort 6 data direction register h?fb9 port 6 bit 7 6 5 4 3 2 1 0 p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 6 input/output control 0 input port 1 output port p6dr?ort 6 data register h?fbb port 6 bit 7 6 5 4 3 2 1 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p7dr?ort 7 data register h?fbe port 7 bit 7 6 5 4 3 2 1 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value * * * * * * * * read/write r r r r r r r r * depends on the levels of pins p7 7 to p7 0 . 320 p8ddr?ort 8 data direction register h?fbd port 8 bit 7 6 5 4 3 2 1 0 p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr initial value modes 1 and 2 1 0 0 0 0 0 0 1 mode 3 1 0 0 0 0 0 0 0 read/write w w w w w w w port 8 input/output control 0 input port 1 output port p8dr?ort 8 data register h?fbf port 8 bit 7 6 5 4 3 2 1 0 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 initial value 1 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w p9ddr?ort 9 data direction register h?fc0 port 9 bit 7 6 5 4 3 2 1 0 p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr modes 1 and 2 initial value 0 1 0 0 0 0 0 0 read/write w w w w w w w mode 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 9 input/output control 0 input port 1 output port 321 p9dr?ort 9 data register h?fc1 port 9 bit 7 6 5 4 3 2 1 0 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w syscr?ystem control register h?fc4 system control bit 7 6 5 4 3 2 1 0 ssby sts2 sts1 sts0 nmieg dpme rame initial value 0 0 0 0 1 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w ram enable 0 on-chip ram is disabled. 1 on-chip ram is enabled. dual-port ram enable 0 dual-port ram is disabled. 1 (1) single-chip mode: dual-port ram is enabled. (2) expanded modes: no effect nmi edge 0 falling edge of nmi is detected. 1 rising edge of nmi is detected. standby timer select 0 0 0 clock settling time = 8192 states 0 0 1 clock settling time = 16384 states 0 1 0 clock settling time = 32768 states 0 1 1 clock settling time = 65536 states 1 ? ? clock settling time = 131072 states software standby 0 sleep instruction causes transition to sleep mode. 1 sleep instruction causes transition to software standby mode. 322 mdcr?ode control register h?fc5 system control bit 7 6 5 4 3 2 1 0 mds1 mds0 initial value 1 1 1 0 0 1 * * read/write r r mode select bits value at mode pins. * determined by inputs at pins md 1 and md 0 . iscr?rq sense control register h?fc6 system control bit 7 6 5 4 3 2 1 0 irq 7 sc irq 6 sc irq 5 sc irq 4 sc irq 3 sc irq 2 sc irq 1 sc irq 0 sc initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w irq 0 to irq 7 sense control 0 irq i is level-sensed (active low). 1 irq i is edge-sensed (falling edge). ier?rq enable register h?fc7 system control bit 7 6 5 4 3 2 1 0 irq 7 e irq 6 e irq 5 e irq 4 e irq 3 e irq 2 e irq 1 e irq 0 e initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w irq 0 to irq 7 enable 0 irq i is disabled. 1 irq i is enabled. 323 tcr?imer control register h?fc8 tmr0 bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w clock select 0 0 0 no clock source; timer stops. 0 0 1 internal clock source: /8, counted on falling edge. 0 1 0 internal clock source: /64, counted on falling edge. 0 1 1 internal clock source: /1024, counted on falling edge. 1 0 0 no clock source; timer stops. 1 0 1 external clock source, counted on rising edge. 1 1 0 external clock source, counted on falling edge. 1 1 1 external clock source, counted on both rising and falling edges. counter clear 0 0 counter is not cleared. 0 1 cleared by compare-match a. 1 0 cleared by compare-match b. 1 1 cleared on rising edge of external reset input. timer overflow interrupt enable 0 overflow interrupt request is disabled. 1 overflow interrupt request is enabled. compare-match interrupt enable a 0 compare-match a interrupt request is disabled. 1 compare-match a interrupt request is enabled. compare-match interrupt enable b 0 compare-match b interrupt request is disabled. 1 compare-match b interrupt request is enabled. 324 tcsr?imer control/status register h?fc9 tmr0 bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3* 2 os2* 2 os1* 2 os0* 2 initial value 0 0 0 1 0 0 0 0 read/write r/(w)* 1 r/(w)* 1 r/(w)* 1 r/w r/w r/w r/w output select 0 0 no change on compare-match a. 0 1 output ??on compare-match a. 1 0 output ??on compare-match a. 1 1 invert (toggle) output on compare-match a. output select 0 0 no change on compare-match b. 0 1 output ??on compare-match b. 1 0 output ??on compare-match b. 1 1 invert (toggle) output on compare-match b. timer overflow flag 0 cleared when cpu reads ovf = ?,?then writes ??in ovf. 1 set when tcnt changes from h?f to h?0. compare-match flag a 0 cleared when cpu reads cmfa = ?,?then writes ??in cmfa. 1 set when tcnt = tcora. compare-match flag b 0 cleared from when cpu reads cmfb = ?,?then writes ??in cmfb. 1 set when tcnt = tcorb. * 1 software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. * 2 when all four bits (os3 to os0) are cleared to ?,?output is disabled. 325 tcora?ime constant register a h?fca tmr0 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the cmfa bit is set to ??when tcora = tcnt. tcorb?ime constant register b h?fcb tmr0 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the cmfb bit is set to ??when tcorb = tcnt. tcnt?imer counter h?fcc tmr0 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value tcr?imer control register h?fd0 tmr1 bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for tmr0. 326 tcsr?imer control/status register h?fd1 tmr1 bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3* 2 os2* 2 os1* 2 os0* 2 initial value 0 0 0 1 0 0 0 0 read/write r/(w)* 1 r/(w)* 1 r/(w)* 1 r/w r/w r/w r/w note: bit functions are the same as for tmr0. * 1 software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. * 2 when all four bits (os3 to os0) are cleared to ?,?output is disabled. tcora?ime constant register a h?fd2 tmr1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for tmr0. tcorb?ime constant register b h?fd3 tmr1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for tmr0. tcnt?imer counter h?fd4 tmr1 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for tmr0. 327 smr?erial mode register h?fd8 sci bit 7 6 5 4 3 2 1 0 c/a chr pe o/e stop cks1 cks0 initial value 0 0 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w clock select 0 0 clock 0 1 /4 clock 1 0 /16 clock 1 1 /64 clock stop bit length 0 one stop bit 1 two stop bits parity mode 0 even parity 1 odd parity parity enable 0 transmit: no parity bit added. receive: parity bit not checked. 1 transmit: parity bit added. receive: parity bit checked. character length 0 8-bit data length 1 7-bit data length communication mode 0 asynchronous 1 synchronous 328 brr?it rate register h?fd9 sci bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w constant that determines the bit rate scr?erial control register h?fda sci bit 7 6 5 4 3 2 1 0 tie rie te re cke1 cke0 initial value 0 0 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w clock enable 0 0 asynchronous serial clock not output 1 asynchronous serial clock output at asck pin clock enable 1 0 internal clock 1 external clock, input at asck or csck pin receive enable 0 receive disabled 1 receive enabled transmit enable 0 transmit disabled 1 transmit enabled receive interrupt enable 0 receive interrupt request (rxi) is disabled. 1 receive interrupt request (rxi) is enabled. transmit interrupt enable 0 transmit interrupt request (txi) is disabled. 1 transmit interrupt request (txi) is enabled. 329 tdr?ransmit data register h?fdb sci bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w transmit data 330 ssr?erial status register h?fdc sci bit 7 6 5 4 3 2 1 0 tdre rdrf orer fer per initial value 1 0 0 0 0 1 1 1 read/write r/(w)* r/(w)* r/(w)* r/(w)* r/(w)* parity error 0 cleared when cpu reads per = ?,?then writes ??in per. 1 set when a parity error occurs (parity of receive data does not match parity selected by o/e bit). framing error 0 cleared when cpu reads fer = ?,?then writes ??in fer. 1 set when a framing error occurs (stop bit is ??. overrun error 0 cleared when cpu reads orer = ?,?then writes ??in orer. 1 set when an overrun error occurs (next data is completely received while rdrf bit is set to ??. receive data register full 0 cleared when cpu reads rdrf = ?,?then writes ??in rdrf. 1 set when one character is received normally and transferred from rsr to rdr. transmit data register empty 0 cleared when cpu reads tdre = ?,?then writes ??in tdre 1 set when: 1. data is transferred from tdr to tsr. 2. te is cleared while tdre = "0." * software can write a ??in bits 7 to 3 to clear the flags, but cannot write a ??in these bits. rdr?eceive data register h?fdd sci bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r receive data 331 addrn?/d data register n (n = a, b, c, d) a/d h?fe0, h?fe2, h?fe4, h?fe6 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r a/d conversion result note: the least significant bit of the register address is ignored. 332 adcsr?/d control/status register h?fe8 a/d bit 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 read/write r/(w)* r/w r/w r/w r/w r/w r/w r/w channel select ch2 ch1 ch0 single mode scan mode 0 0 0 an 0 an 0 0 1 an 1 an 0 , an 1 1 0 an 2 an 0 to an 2 1 1 an 3 an 0 to an 3 1 0 0 an 4 an 4 0 1 an 5 an 4 , an 5 1 0 an 6 an 4 to an 6 1 1 an 7 an 4 to an 7 clock select 0 conversion time = 242 states (max) 1 conversion time = 122 states (max) scan mode 0 single mode 1 scan mode a/d start 0 a/d conversion is halted. 1 1. single mode: one a/d conversion is performed, then this bit is automatically cleared to ?. 2. scan mode: a/d conversion starts and continues cyclically on all selected channels until ?? is written in this bit. a/d interrupt enable 0 the a/d interrupt request (adi) is disabled. 1 the a/d interrupt request (adi) is enabled. a/d end flag 0 cleared from ??to ??when cpu reads adf = ?,?then writes ??in adf. 1 set to ??at the following times: 1. single mode: at the completion of a/d conversion 2. scan mode: when all selected channels have been converted. * software can write a ??in bit 7 to clear the flag, but cannot write a ??in this bit. 333 adcr?/d control register h?fea or h?feb a/d bit 7 6 5 4 3 2 1 0 trge initial value 0 1 1 1 1 1 1 1 read/write r/w trigger enable 0 adtrg is disabled. 1 adtrg is enabled. a/d conversion can be started by external trigger, or by software. 334 pccsr?arallel communication control/status register h?ff0 dpram bit 7 6 5 4 3 2 1 0 mwef emwi swef eakar mref emri mwmf swmf initial value 0 0 0 0 0 0 0 0 read/write h8/300 cpu: r r/w r r/w r r/w r r master cpu: r r r r/w r r r r master write end flag 0 h8/300 cpu has read pcdr14 while mwmf = "1." 1 master cpu has written data in pcdr14. enable master write interrupt 0 master write end interrupt (mwei) is disabled. 1 master write end interrupt (mwei) is enabled. slave write end flag 0 master cpu has read pcdr14. 1 h8/300 cpu has written data in pcdr14. enable acknowledge and request 0 rdy output is disabled. remains in high-impedance state. 1 rdy output is enabled. master read end flag 0 cleared when h8/300 cpu reads or writes pcdr0, or master cpu writes to pcdr0. 1 set when master cpu reads pcdr0. enable master read interrupt 0 master read end interrupt (mrei) is disabled. 1 master read end interrupt (mrei) is enabled. master write mode flag 0 not master write mode. cleared when h8/300 cpu reads pcdr0. 1 master write mode. set if the master cpu writes to pcdr0 while swmf = ?. slave write mode flag 0 not slave write mode. cleared when master cpu reads pcdr0. 1 slave write mode. set if h8/300 cpu writes to pcdr0 while mwmf = ?. 335 pcdr0a?arallel communication data register 0a h?ff1 dpram bit 7 6 5 4 3 2 1 0 initial value read/write h8/300 cpu: r r r r r r r r master cpu: w w w w w w w w pcdr0b?arallel communication data register 0b h?ff1 dpram bit 7 6 5 4 3 2 1 0 initial value read/write h8/300 cpu: w w w w w w w w master cpu: r r r r r r r r pcdr1 to pcdr14?arallel communication data registers 1 to 14 h?ff2 ?h?fff dpram bit 7 6 5 4 3 2 1 0 initial value read/write h8/300 cpu:r/w r/w r/w r/w r/w r/w r/w r/w master cpu: r/w r/w r/w r/w r/w r/w r/w r/w 336 appendix c. pin states c.1 pin states in each mode table c-1. pin states pin mcu hardware software sleep normal name mode reset standby standby mode operation p1 7 ?p1 0 1 low 3-state low prev. state addr. output a 7 ?a 0 2 3-state low if (addr. addr. output ddr = 1, output pins: or input port prev. state last address if ddr = 0 accessed) 3 prev. state i/o port p2 7 ?p2 0 1 low 3-state low prev. state addr. output a 15 ?a 8 2 3-state low if (addr. addr. output ddr = 1, output pins: or input port prev. state last address if ddr = 0 accessed) 3 prev. state i/o port p3 7 ?p3 0 1 3-state 3-state 3-state 3-state d 7 ?d 0 d 7 ?d 0 2 3 prev. state prev. state i/o port p4 7 ?p4 0 , 1 3-state 3-state prev. state prev. state i/o port 2 (note 3) 3 p5 2 ?p5 0 , 1 3-state 3-state prev. state prev. state i/o port 2 (note 3) 3 p6 7 ?p6 0 , 1 3-state 3-state prev. state prev. state i/o port 2 (note 3) 3 p7 7 ?p7 0, 1 3-state 3-state 3-state 3-state input port 2 3 p8 6 ?p8 1 , 1 3-state 3-state prev. state prev. state i/o port 2 (note 3) 3 337 table c-1. pin states (cont.) pin mcu hardware software sleep normal name mode reset standby standby mode operation p8 0 /e 1 e clock 3-state low if e clock if e clock if 2 output ddr = 1, ddr = 1, ddr = 1, 3-state if 3-state if 3-state if ddr = 0 ddr = 0 ddr = 0 3 3-state prev. state prev. state i/o port p9 7 /wait 1 3-state 3-state 3-state 3-state wait 2 3 prev. state prev. state i/o port p9 6 / 1 clock 3-state high clock clock 2 output output output 3 3-state high if clock output clock output ddr = 1, if ddr = 1, if ddr = 1, 3-state if 3-state if input port if ddr = 0 ddr = 0 ddr = 0 p9 5 ?p9 3 , 1 high 3-state high high as, wr, as, wr, rd 2 rd 3 3-state prev. state prev. state i/o port p9 2 ?p9 0 , 1 3-state 3-state prev. state prev. state i/o port 2 3 notes: 1. 3-state: high-impedance state 2. prev. state: previous state. input ports are in the high-impedance state (with the mos pull-up on if ddr = 0 and dr = 1). output ports hold their previous output level. 3. on-chip supporting modules are initialized, so these pins revert to i/o ports according to the ddr and dr bits. 4. i/o port: direction depends on the data direction (ddr) bit. note that these pins may also be used by the on-chip supporting modules. see section 5, ?/o ports?for further information. 338 appendix d. timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1). to retain ram contents, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). (2). when it is not necessary to retain ram contents, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. stby res t = 100 ns t osc stby res t 10 t 1 cyc t 0 ns 2 339 appendix e. package dimensions figure e-1 shows the dimensions of the cg-84 package. figure e-2 shows the dimensions of the cp-84 package. figure e-3 shows the dimensions of the fp-80a package. unit: mm figure e-1. package dimensions (cg-84) unit: mm figure e-2. package dimensions (cp-84) 1.27 0.42 ?0.10 29.28 28.20 ?0.50 28.20 ?0.50 4.40 ?0.20 2.55 ?0.15 0.10 30.23 ?0.12 53 33 54 74 75 84 1 11 12 32 30.23 ?0.12 0.75 29.21 ?0.38 2.16 1.27 12 32 11 33 1 84 75 53 74 54 1.27 0.635 4.03 max f d unit: mm figure e-3. package dimensions (fp-80a) 60 0 ?5 0.10 0.12 m 17.2 ?0.3 41 61 80 1 20 40 21 17.2 ?.3 0.30 ?.10 0.65 3.05 max 0.10 1.60 0.80 ?0.30 14.0 2.70 +0.20 ?.16 0.17 +0.08 ?.05 |
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